A Chip Level Cdm Esd Protection Circuit Modeling And Simulation Method And Experimental Verification
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A Chip Level Cdm Esd Protection Circuit Modeling And Simulation Method And Experimental Verification
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Author : Han Wang
language : en
Publisher:
Release Date : 2018
A Chip Level Cdm Esd Protection Circuit Modeling And Simulation Method And Experimental Verification written by Han Wang and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2018 with Electric discharges categories.
This thesis describes a novel distributed electrostatic charge distribution model and a new circuit-level simulation method to enable accurate full-chip CDM ESD protection circuit simulation, aiming to achieve CDM ESD protection design prediction and hence, first-Silicon design success in developing CDM ESD protection solutions for advanced ICs. The new CDM ESD model and simulation techniques developed was verified in ICs implemented in a commercial 28nm CMOS technology.
Design Characterization And Compact Modeling Of Novel Silicon Controlled Rectifier Scr Based Devices For Electrostatic Discharge Esd Protection Applications In Integrated Circuits
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Author : Lifang Lou
language : en
Publisher:
Release Date : 2008
Design Characterization And Compact Modeling Of Novel Silicon Controlled Rectifier Scr Based Devices For Electrostatic Discharge Esd Protection Applications In Integrated Circuits written by Lifang Lou and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2008 with Electric discharges categories.
Electrostatic Discharge (ESD), an event of a sudden transfer of electrons between two bodies at different potentials, happens commonly throughout nature. When such even occurs on integrated circuits (ICs), ICs will be damaged and failures result. As the evolution of semiconductor technologies, increasing usage of automated equipments and the emerging of more and more complex circuit applications, ICs are more sensitive to ESD strikes. Main ESD events occurring in semiconductor industry have been standardized as human body model (HBM), machine model (MM), charged device model (CDM) and international electrotechnical commission model (IEC) for control, monitor and test. In additional to the environmental control of ESD events during manufacturing, shipping and assembly, incorporating on-chip ESD protection circuits inside ICs is another effective solution to reduce the ESD-induced damage. This dissertation presents design, characterization, integration and compact modeling of novel silicon controlled rectifier (SCR)-based devices for on-chip ESD protection. The SCR-based device with a snapback characteristic has long been used to form a V[subscript SS]-based protection scheme for on-chip ESD protection over a broad rang of technologies because of its low on-resistance, high failure current and the best area efficiency. The ESD design window of the snapback device is defined by the maximum power supply voltage as the low edge and the minimum internal circuitry breakdown voltage as the high edge. The downscaling of semiconductor technology keeps on squeezing the design window of on-chip ESD protection. For the submicron process and below, the turn-on voltage and sustain voltage of ESD protection cell should be lower than 10 V and higher than 5 V, respectively, to avoid core circuit damages and latch-up issue. This presents a big challenge to device/circuit engineers. Meanwhile, the high voltage technologies push the design window to another tough range whose sustain voltage, 45 V for instance, is hard for most snapback ESD devices to reach. Based on the in-depth elaborating on the principle of SCR-based devices, this dissertation first presents a novel unassisted, low trigger- and high holding-voltage SCR (uSCR) which can fit into the aforesaid ESD design window without involving any extra assistant circuitry to realize an area-efficient on-chip ESD protection for low voltage applications. The on-chip integration case is studied to verify the protection effectiveness of the design. Subsequently, this dissertation illustrate the development of a new high holding current SCR (HHC-SCR) device for high voltage ESD protection with increasing the sustain current, not the sustain voltage, of the SCR device to the latchup-immune level to avoid sacrificing the ESD protection robustness of the device. The ESD protection cells have been designed either by using technology computer aided design (TCAD) tools or through trial-and-error iterations, which is cost- or time-consuming or both. Also, the interaction of ESD protection cells and core circuits need to be identified and minimized at pre-silicon stage. It is highly desired to design and evaluate the ESD protection cell using simulation program with integrated circuit emphasis (SPICE)-like circuit simulation by employing compact models in circuit simulators. And the compact model also need to predict the response of ESD protection cells to very fast transient ESD events such as CDM event since it is a major ESD failure mode. The compact model for SCR-based device is not widely available. This dissertation develops a macromodeling approach to build a comprehensive SCR compact model for CDM ESD simulation of complete I/O circuit. This modeling approach offers simplicity, wide availability and compatibility with most commercial simulators by taking advantage of using the advanced BJT model, Vertical Bipolar Inter-Company (VBIC) model. SPICE Gummel-Poon (SGP) model has served the ICs industry well for over 20 years while it is not sufficiently accurate when using SGP model to build a compact model for ESD protection SCR. This dissertation seeks to compare the difference of SCR compact model built by using VBIC and conventional SGP in order to point out the important features of VBIC model for building an accurate and easy-CAD implement SCR model and explain why from device physics and model theory perspectives.
Simulation Methods For Esd Protection Development
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Author : Harald Gossner
language : en
Publisher: Elsevier
Release Date : 2003-10-16
Simulation Methods For Esd Protection Development written by Harald Gossner and has been published by Elsevier this book supported file pdf, txt, epub, kindle and other format this book has been release on 2003-10-16 with Science categories.
Simulation Methods for ESD Protection Development looks at the integration of new techniques into a comprehensive development flow, which is now available due advances made in the field during the recent years. These findings allow for an early, stable ESD concept at a very early stage of the technology development, which is essential now development cycles have been reduced. The book also offers ways of increasing the optimization and control of the technology concerning performance, thus making the process more cost effective and increasingly efficient. This title provides a guide through the latest research and technology presenting the ESD protection development methodology. This is based on a combination of process, device and circuit stimulation, and addresses the optimization of the industry critical issue, reduced development cycles.Written to address the needs of the ESD engineer, this text is required reading by all industry practitioners and researchers and students within this field. The FIRST Extensive overview on the subject of ESD simulation Addresses the industry critical issue of reduced development cycles, and provides solutions Presents the latest research in the field with high practical relevance and its results
Full Chip Modeling For Predictive Simulation Of Charged Device Model Electrostatic Discharge Events
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Author : Vrashank G. Shukla
language : en
Publisher:
Release Date : 2010
Full Chip Modeling For Predictive Simulation Of Charged Device Model Electrostatic Discharge Events written by Vrashank G. Shukla and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2010 with categories.
With downscaling of device dimensions in integrated circuits (ICs), the risk of circuit failure due to electrostatic discharge (ESD) is increasing. In particular, the increased usage of automated handlers is causing charged device model (CDM) ESD induced failures to become more prominent. Gate oxide failure is the primary signature of CDM ESD. During CDM, the IC is the source as well as the path for the static charge. Therefore, it is important to include the circuit elements representing the package, ESD circuits and the silicon substrate of the packaged ICs. Power domain crossing circuits, also known as internal I/Os, are susceptible to gate oxide damage during CDM events. In this thesis, circuit-level simulations of internal I/O circuits are used to elucidate the roles of the package, power clamp placement, anti-parallel diode placement and decoupling capacitors in determining the amount of stress at the internal I/O circuits. This thesis will also provide design recommendations for preventing CDM failures in the internal I/O circuits.
Electrical Overstress Electrostatic Discharge Symposium Proceedings
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Author :
language : en
Publisher:
Release Date : 2004
Electrical Overstress Electrostatic Discharge Symposium Proceedings written by and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2004 with Electric discharges categories.
Design Of Low Capacitance And High Speed Electrostatic Discharge Esd Devices For Low Voltage Protection Applications
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Author : You Li
language : en
Publisher:
Release Date : 2010
Design Of Low Capacitance And High Speed Electrostatic Discharge Esd Devices For Low Voltage Protection Applications written by You Li and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2010 with Electric capacity categories.
Electrostatic discharge (ESD) is defined as the transfer of charge between bodies at different potentials. The electrostatic discharge induced integrated circuit damages occur throughout the whole life of a product from the manufacturing, testing, shipping, handing, to end user operating stages. This is particularly true as microelectronics technology continues shrink to nano-metric dimensions. The ESD related failures is a major IC reliability concern and results in a loss of millions dollars to the semiconductor industry each year. Several ESD stress models and test methods have been developed to reproduce the real world ESD discharge events and quantify the sensitivity of ESD protection structures. The basic ESD models are: Human body model (HBM), Machine model (MM), and Charged device model (CDM). To avoid or reduce the IC failure due to ESD, the on-chip ESD protection structures and schemes have been implemented to discharge ESD current and clamp overstress voltage under different ESD stress events. Because of its simple structure and good performance, the junction diode is widely used in on-chip ESD protection applications. This is particularly true for ESD protection of low-voltage ICs where a relatively low trigger voltage for the ESD protection device is required. However, when the diode operates under the ESD stress, its current density and temperature are far beyond the normal conditions and the device is in danger of being damaged. For the design of effective ESD protection solution, the ESD robustness and low parasitic capacitance are two major concerns. The ESD robustness is usually defined after the failure current It2 and on-state resistance Ron. The transmission line pulsing (TLP) measurement is a very effective tool for evaluating the ESD robustness of a circuit or single element. This is particularly helpful in characterizing the effect of HBM stress where the ESD-induced damages are more likely due to thermal failures. Two types of diodes with different anode/cathode isolation technologies will be investigated for their ESD performance: one with a LOCOS (Local Oxidation of Silicon) oxide isolation called the LOCOS-bound diode, the other with a polysilicon gate isolation called the polysilicon-bound diode. We first examine the ESD performance of the LOCOS-bound diode. The effects of different diode geometries, metal connection patterns, dimensions and junction configurations on the ESD robustness and parasitic capacitance are investigated experimentally. The devices considered are N+/P-well junction LOCOS-bound diodes having different device widths, lengths and finger numbers, but the approach applies generally to the P+/N-well junction diode as well. The results provide useful insights into optimizing the diode for robust HBM ESD protection applications. Then, the current carrying and voltage clamping capabilities of LOCOS- and polysilicon-bound diodes are compared and investigated based on both TCAD simulation and experimental results. Comparison of these capabilities leads to the conclusion that the polysilicon-bound diode is more suited for ESD protection applications due to its higher performance. The effects of polysilicon-bound diode's design parameters, including the device width, anode/cathode length, finger number, poly-gate length, terminal connection and metal topology, on the ESD robustness are studied. Two figures of merits, FOM_It2 and FOM_Ron, are developed to better assess the effects of different parameters on polysilicon-bound diode's overall ESD performance. As latest generation package styles such as mBGAs, SOTs, SC70s, and CSPs are going to the millimeter-range dimensions, they are often effectively too small for people to handle with fingers. The recent industry data indicates the charged device model (CDM) ESD event becomes increasingly important in today's manufacturing environment and packaging technology. This event generates highly destructive pulses with a very short rise time and very small duration. TLP has been modified to probe CDM ESD protection effectiveness. The pulse width was reduced to the range of 1-10 ns to mimic the very fast transient of the CDM pulses. Such a very fast TLP (VFTLP) testing has been used frequently for CDM ESD characterization. The overshoot voltage and turn-on time are two key considerations for designing the CDM ESD protection devices. A relatively high overshoot voltage can cause failure of the protection devices as well as the protected devices, and a relatively long turn-on time may not switch on the protection device fast enough to effectively protect the core circuit against the CDM stress. The overshoot voltage and turn-on time of an ESD protection device can be observed and extracted from the voltage versus time waveforms measured from the VFTLP testing. Transient behaviors of polysilicon-bound diodes subject to pulses generated by the VFTLP tester are characterized for fast ESD events such as the charged device model. The effects of changing devices' dimension parameters on the transient behaviors and on the overshoot voltage and turn-on time are studied. The correlation between the diode failure and poly-gate configuration under the VFTLP stress is also investigated. Silicon-controlled rectifier (SCR) is another widely used ESD device for protecting the I/O pins and power supply rails of integrated circuits. Multiple fingers are often needed to achieve optimal ESD protection performance, but the uniformity of finger triggering and current flow is always a concern for multi-finger SCR devices operating under the post-snapback region. Without a proper understanding of the finger turn-on mechanism, design and realization of robust SCRs for ESD protection applications are not possible. Two two-finger SCRs with different combinations of anode/cathode regions are considered, and their finger turn-on uniformities are analyzed based on the I-V characteristics obtained from the transmission line pulsing (TLP) tester. The dV/dt effect of pulses with different rise times on the finger turn-on behavior of the SCRs are also investigated experimentally. In this work, unless noted otherwise, all the measurements are conducted using the Barth 4002 transmission line pulsing (TLP) and Barth 4012 very-fast transmission line pulsing (VFTLP) testers.
Esd
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Author : Steven H. Voldman
language : en
Publisher: John Wiley & Sons
Release Date : 2009-07-01
Esd written by Steven H. Voldman and has been published by John Wiley & Sons this book supported file pdf, txt, epub, kindle and other format this book has been release on 2009-07-01 with Technology & Engineering categories.
Electrostatic discharge (ESD) failure mechanisms continue to impact semiconductor components and systems as technologies scale from micro- to nano-electronics. This book studies electrical overstress, ESD, and latchup from a failure analysis and case-study approach. It provides a clear insight into the physics of failure from a generalist perspective, followed by investigation of failure mechanisms in specific technologies, circuits, and systems. The book is unique in covering both the failure mechanism and the practical solutions to fix the problem from either a technology or circuit methodology. Look inside for extensive coverage on: failure analysis tools, EOS and ESD failure sources and failure models of semiconductor technology, and how to use failure analysis to design more robust semiconductor components and systems; electro-thermal models and technologies; the state-of-the-art technologies discussed include CMOS, BiCMOS, silicon on insulator (SOI), bipolar technology, high voltage CMOS (HVCMOS), RF CMOS, smart power, gallium arsenide (GaAs), gallium nitride (GaN), magneto-resistive (MR) , giant magneto-resistors (GMR), tunneling magneto-resistor (TMR), devices; micro electro-mechanical (MEM) systems, and photo-masks and reticles; practical methods to use failure analysis for the understanding of ESD circuit operation, temperature analysis, power distribution, ground rule development, internal bus distribution, current path analysis, quality metrics, (connecting the theoretical to the practical analysis); the failure of each key element of a technology from passives, active elements to the circuit, sub-system to package, highlighted by case studies of the elements, circuits and system-on-chip (SOC) in today’s products. ESD: Failure Mechanisms and Models is a continuation of the author’s series of books on ESD protection. It is an essential reference and a useful insight into the issues that confront modern technology as we enter the Nano-electronic era.
Dissertation Abstracts International
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Author :
language : en
Publisher:
Release Date : 2002
Dissertation Abstracts International written by and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2002 with Dissertations, Academic categories.
On Chip Esd Protection For Integrated Circuits
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Author : Albert Z.H. Wang
language : en
Publisher: Springer Science & Business Media
Release Date : 2006-01-03
On Chip Esd Protection For Integrated Circuits written by Albert Z.H. Wang and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2006-01-03 with Technology & Engineering categories.
This comprehensive and insightful book discusses ESD protection circuit design problems from an IC designer's perspective. On-Chip ESD Protection for Integrated Circuits: An IC Design Perspective provides both fundamental and advanced materials needed by a circuit designer for designing ESD protection circuits, including: Testing models and standards adopted by U.S. Department of Defense, EIA/JEDEC, ESD Association, Automotive Electronics Council, International Electrotechnical Commission, etc. ESD failure analysis, protection devices, and protection of sub-circuits Whole-chip ESD protection and ESD-to-circuit interactions Advanced low-parasitic compact ESD protection structures for RF and mixed-signal IC's Mixed-mode ESD simulation-design methodologies for design prediction ESD-to-circuit interactions, and more! Many real world ESD protection circuit design examples are provided. The book can be used as a reference book for working IC designers and as a textbook for students in the IC design field.
System Level Esd Protection
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Author : Vladislav Vashchenko
language : en
Publisher: Springer Science & Business Media
Release Date : 2014-03-21
System Level Esd Protection written by Vladislav Vashchenko and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2014-03-21 with Technology & Engineering categories.
This book addresses key aspects of analog integrated circuits and systems design related to system level electrostatic discharge (ESD) protection. It is an invaluable reference for anyone developing systems-on-chip (SoC) and systems-on-package (SoP), integrated with system-level ESD protection. The book focuses on both the design of semiconductor integrated circuit (IC) components with embedded, on-chip system level protection and IC-system co-design. The readers will be enabled to bring the system level ESD protection solutions to the level of integrated circuits, thereby reducing or completely eliminating the need for additional, discrete components on the printed circuit board (PCB) and meeting system-level ESD requirements. The authors take a systematic approach, based on IC-system ESD protection co-design. A detailed description of the available IC-level ESD testing methods is provided, together with a discussion of the correlation between IC-level and system-level ESD testing methods. The IC-level ESD protection design is demonstrated with representative case studies which are analyzed with various numerical simulations and ESD testing. The overall methodology for IC-system ESD co-design is presented as a step-by-step procedure that involves both ESD testing and numerical simulations.