Improved Architectures For Fused Floating Point Arithmetic Units
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Improved Architectures For Fused Floating Point Arithmetic Units
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Author : Jongwook Sohn
language : en
Publisher:
Release Date : 2013
Improved Architectures For Fused Floating Point Arithmetic Units written by Jongwook Sohn and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2013 with categories.
Most general purpose processors (GPP) and application specific processors (ASP) use the floating-point arithmetic due to its wide and precise number system. However, the floating-point operations require complex processes such as alignment, normalization and rounding. To reduce the overhead, fused floating-point arithmetic units are introduced. In this dissertation, improved architectures for three fused floating-point arithmetic units are proposed: 1) Fused floating-point add-subtract unit, 2) Fused floating-point two-term dot product unit, and 3) Fused floating-point three-term adder. Also, the three fused floating-point units are implemented for both single and double precision and evaluated in terms of the area, power consumption, latency and throughput. To improve the performance of the fused floating-point add-subtract unit, a new alignment scheme, fast rounding, two dual-path algorithms and pipelining are applied. The improved fused floating-point two-term dot product unit applies several optimizations: a new alignment scheme, early normalization and fast rounding, four-input leading zero anticipation (LZA), dual-path algorithm and pipelining. The proposed fused floating-point three-term adder applies a new exponent compare and significand alignment scheme, double reduction, early normalization and fast rounding, three-input LZA and pipelining to improve the performance.
Improved Architectures For A Fused Floating Point Add Subtract Unit
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Author : Jongwook Sohn
language : en
Publisher:
Release Date : 2011
Improved Architectures For A Fused Floating Point Add Subtract Unit written by Jongwook Sohn and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2011 with categories.
This report presents improved architecture designs and implementations for a fused floating-point add-subtract unit. The fused floating-point add-subtract unit is useful for DSP applications such as FFT and DCT butterfly operations. To improve the performance of the fused floating-point add-subtract unit, the dual path algorithm and pipelining technique are applied. The proposed designs are implemented for both single and double precision and synthesized with a 45nm standard-cell library. The fused floating-point add-subtract unit saves 40% of the area and power consumption and the dual path fused floating-point add-subtract unit reduces the latency by 30% compared to the traditional discrete floating-point add-subtract unit. By combining fused operation and the dual path design, the proposed floating-point add-subtract unit achieves low area, low power consumption and high speed. Based on the data flow analysis, the proposed fused floating-point add-subtract unit is split into two pipeline stages. Since the latencies of two pipeline stages are fairly well balanced the throughput of the entire logic is increased by 80% compared to the non-pipelined implementation.
Fused Floating Point Arithmetic For Application Specific Processors
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Author : Jae Hong Min
language : en
Publisher:
Release Date : 2013
Fused Floating Point Arithmetic For Application Specific Processors written by Jae Hong Min and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2013 with categories.
Floating-point computer arithmetic units are used for modern-day computers for 2D/3D graphic and scientific applications due to their wider dynamic range than a fixed-point number system with the same word-length. However, the floating-point arithmetic unit has larger area, power consumption, and latency than a fixed-point arithmetic unit. It has become a big issue in modern low-power processors due to their limited power and performance margins. Therefore, fused architectures have been developed to improve floating-point operations. This dissertation introduces new improved fused architectures for add-subtract, sum-of-squares, and magnitude operations for graphics, scientific, and signal processing. A low-power dual-path fused floating-point add-subtract unit is introduced and compared with previous fused add-subtract units such as the single path and the high-speed dual-path fused add-subtract unit. The high-speed dual-path fused add-subtract unit has less latency compared with the single-path unit at a cost of large power consumption. To reduce the power consumption, an alternative dual-path architecture is applied to the fused add-subtract unit. The significand addition, subtraction and round units are performed after the far/close path. The power consumption of the proposed design is lower than the high-speed dual-path fused add-subtract unit at a cost in latency; however, the proposed fused unit is faster than the single-path fused unit. High-performance and low-power floating-point fused architectures for a two-term sum-of-squares computation are introduced and compared with discrete units. The fused architectures include pre/post-alignment, partial carry-sum width, and enhanced rounding. The fused floating-point sum-of-squares units with the post-alignment, 26 bit partial carry-sum width, and enhanced rounding system have less power-consumption, area, and latency compared with discrete parallel dot-product and sum-of-squares units. Hardware tradeoffs are presented between the fused designs in terms of power consumption, area, and latency. For example, the enhanced rounding processing reduces latency with a moderate cost of increased power consumption and area. A new type of fused architecture for magnitude computation with less power consumption, area, and latency than conventional discrete floating-point units is proposed. Compared with the discrete parallel magnitude unit realized with conventional floating-point squarers, an adder, and a square-root unit, the fused floating-point magnitude unit has less area, latency, and power consumption. The new design includes new designs for enhanced exponent, compound add/round, and normalization units. In addition, a pipelined structure for the fused magnitude unit is shown.
Microelectronic Devices Circuits And Systems
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Author : V. Arunachalam
language : en
Publisher: Springer Nature
Release Date : 2021-08-02
Microelectronic Devices Circuits And Systems written by V. Arunachalam and has been published by Springer Nature this book supported file pdf, txt, epub, kindle and other format this book has been release on 2021-08-02 with Computers categories.
This book constitutes selected papers from the Second International Conference on Microelectronic Devices, Circuits and Systems, ICMDCS 2021, held in Vellore, India, in February 2021. The 32 full papers and 6 short papers presented were thoroughly reviewed and selected from 103 submissions. They are organized in the topical sections on digital design for signal, image and video processing; VLSI testing and verification; emerging technologies and IoT; nano-scale modelling and process technology device; analog and mixed signal design; communication technologies and circuits; technology and modelling for micro electronic devices; electronics for green technology.
Proceedings Of The Second International Conference On Soft Computing For Problem Solving Socpros 2012 December 28 30 2012
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Author : B. V. Babu
language : en
Publisher: Springer
Release Date : 2014-07-08
Proceedings Of The Second International Conference On Soft Computing For Problem Solving Socpros 2012 December 28 30 2012 written by B. V. Babu and has been published by Springer this book supported file pdf, txt, epub, kindle and other format this book has been release on 2014-07-08 with Technology & Engineering categories.
The present book is based on the research papers presented in the International Conference on Soft Computing for Problem Solving (SocProS 2012), held at JK Lakshmipat University, Jaipur, India. This book provides the latest developments in the area of soft computing and covers a variety of topics, including mathematical modeling, image processing, optimization, swarm intelligence, evolutionary algorithms, fuzzy logic, neural networks, forecasting, data mining, etc. The objective of the book is to familiarize the reader with the latest scientific developments that are taking place in various fields and the latest sophisticated problem solving tools that are being developed to deal with the complex and intricate problems that are otherwise difficult to solve by the usual and traditional methods. The book is directed to the researchers and scientists engaged in various fields of Science and Technology.
Fused Floating Point Arithmetic For Dsp
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Author : Hani Hasan Mustafa Saleh
language : en
Publisher:
Release Date : 2009
Fused Floating Point Arithmetic For Dsp written by Hani Hasan Mustafa Saleh and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2009 with Floating-point arithmetic categories.
Floating-point arithmetic is attractive for the implementation for a variety of Digital Signal Processing (DSP) applications because it allows the designer and user to concentrate on the algorithms and architecture without worrying about numerical issues. In the past, many DSP applications used fixed point arithmetic due to the high cost (in delay, silicon area, and power consumption) of floating-point arithmetic units. In the realization of modern general purpose processors, fused floating-point multiply add units have become attractive since their delay and silicon area is often less than that of a discrete floating-point multiplier followed by a floating point adder. Further the accuracy is improved by the fused implementation since rounding is performed only once (after the multiplication and addition). This work extends the consideration of fused floating-point arithmetic to operations that are frequently encountered in DSP. The Fast Fourier Transform is a case in point since it uses a complex butterfly operation. For a radix-2 implementation, the butterfly consists of a complex multiply and the complex addition and subtraction of the same pair of data. For a radix-4 implementation, the butterfly consists of three complex multiplications and eight complex additions and subtractions. Both of these butterfly operations can be implemented with two fused primitives, a fused two-term dot-product unit and a fused add-subtract unit. The fused two-term dot-product multiplies two sets of operands and adds the products as a single operation. The two products do not need to be rounded (only the sum is normalized and rounded) which reduces the delay by about 15% while reducing the silicon area by about 33%. For the add-subtract unit, much of the complexity of a discrete implementation comes from the need to compare the operand exponents and align the significands prior to the add and the subtract operations. For the fused implementation, sharing the comparison and alignment greatly reduces the complexity. The delay and the arithmetic results are the same as if the operations are performed in the conventional manner with a floating-point adder and a separate floating-point subtracter. In this case, the fused implementation is about 20% smaller than the discrete equivalent.
A Novel Low Power Multi Path Double Precision Fused Multiplier Accumulator Architecture
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Author : Mangala Gopal
language : en
Publisher:
Release Date : 2015
A Novel Low Power Multi Path Double Precision Fused Multiplier Accumulator Architecture written by Mangala Gopal and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2015 with categories.
The floating-point fused multiply-add unit has several advantages in a floating-point unit design. This thesis presents the results of the research, design and implementation of a novel architecture for low power double precision floating-point fused multiply-accumulate (FPMAC) unit. This architecture has been designed to provide a simple solution to the high power consumption and high latency found in modern-day fused multiply-add units. The proposed architecture improves the latency of the operation by removing the dependency between operations, thereby adding more parallel operations with minimum hardware overhead. The proposed fused multiplier accumulator architecture reduces the interconnection between components which was found to be dominant among most FPMAC designs. The basic logic blocks, which are part of the multiplier accumulator architecture are individually analyzed and optimized for power and latency. The proposed architecture showed a significant reduction in power and latency when analyzed using the TSMC 180nm process library.
Computer Arithmetic
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Author : Earl E Swartzlander
language : en
Publisher: World Scientific
Release Date : 2015-02-12
Computer Arithmetic written by Earl E Swartzlander and has been published by World Scientific this book supported file pdf, txt, epub, kindle and other format this book has been release on 2015-02-12 with Mathematics categories.
Computer Arithmetic Volume III is a compilation of key papers in computer arithmetic on floating-point arithmetic and design. The intent is to show progress, evolution, and novelty in the area of floating-point arithmetic. This field has made extraordinary progress since the initial software routines on mainframe computers have evolved into hardware implementations in processors spanning a wide range of performance. Nevertheless, these papers pave the way to the understanding of modern day processors design where computer arithmetic are supported by floating-point units. The goal of Volume III is to collect the defining document for floating-point arithmetic and many of the key papers on the implementation of both binary and decimal floating-point arithmetic into a single volume. Although fewer than forty papers are included, their reference lists will direct the interested reader to other excellent work that could not be included here. Volume III is specifically oriented to the needs of designers and users of both general-purpose computers and special-purpose digital processors. The book should also be useful to systems engineers, computer architects, and logic designers. It is also intended to serve as a primary text for a course on floating-point arithmetic, as well as a supplementary text for courses in digital arithmetic and high-speed signal processing. This volume is part of a 3 volume set: Computer Arithmetic Volume I Computer Arithmetic Volume II Computer Arithmetic Volume III The full set is available for sale in a print-only version. Contents:OverviewFloating-Point AdditionFloating-Point MultiplicationRoundingFused Multiply AddFloating-Point DivisionElementary FunctionsDecimal Floating-Point Arithmetic Readership: Graduate students and research professionals interested in computer arithmetic. Key Features:The papers that are included cover the key concepts needed to develop efficient (fast, small and low-power) floating-point processing unitsThe papers include presentations by the initial developers in their own words to better explain the basic techniquesIncludes five papers on decimal floating-point arithmetic, which has been added to the IEEE standardKeywords:Floating-Point Addition;Floating-Point Multiplication;Floating-Point Division;Decimal Floating-Point Arithmetic
Energy Efficient Floating Point Unit Design
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Author : Sameh Rady Sayed Galal
language : en
Publisher:
Release Date : 2012
Energy Efficient Floating Point Unit Design written by Sameh Rady Sayed Galal and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2012 with categories.
Energy-efficient computation is critical for increasing performance in power limited systems. Floating-point performance is of particular interest because of its importance in scientific computing, graphics and multimedia processing. For floating-point applications that have large amounts of data parallelism one should optimize the throughput/sqmm given a power density constraint. We present a method for creating a trade-off curve that can be used to estimate the maximum floating-point performance given a set of area and power constraints. These throughput optimized designs turn out to be different from latency optimized ones and more energy efficient. Looking at floating-point multiply-add units and ignoring register and memory overheads, we find that in a 90nm CMOS technology at 1W/sqmm, one can achieve a performance of 27 GFlops/sqmm single-precision, and 7.5 GFlops/sqmm double-precision. Adding register file overheads reduces the throughput by less than 50% if the compute intensity is high. Since the energy of the basic gates is no longer scaling rapidly, to maintain constant power density with scaling requires moving the overall floating-point architecture to a lower energy/performance point using lower supply voltage, shallower pipelines and more relaxed gate sizing. A 1W/sqmm design at 90nm is a "high-energy" design, so scaling it to a lower energy design in 45 nm still yields a 7x performance gain, while a more balanced 0.1W/sqmm design only speeds up by 3.5x when scaled to 45 nm. Performance scaling below 45 nm rapidly decreases, with a projected improvement of only 2-3x for both power densities when scaling to a 22 nm technology. On the other hand, some floating-point units employed for single threaded performance such as CPU designs are latency sensitive. For such designs a different optimization in the implementation of fused floating-point multiply-add operations can be utilized. By realizing that the average latency of all operations going through the unit is what matters most, an optimized cascade design can reduce the accumulation dependent latency by 2x over a fused design, at a cost of a 13% increase in non-accumulation dependent latency. A simple in-order execution model shows this design is superior in most applications, providing 12% average reduction in floating-point instructions stalls, and improves performance by up to 6%. Simulations of superscalar out-of-order machines show 4% average CPI improvement in 2-way machines and 4.6% in 4-way machines. This feat is achieved by a design architecture called cascade where the addition operation is cascaded after multiplication in comparison to traditional architectures. The cascade design has the same area and energy budget as a traditional FMA.
Handbook Of Floating Point Arithmetic
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Author : Jean-Michel Muller
language : en
Publisher: Birkhäuser
Release Date : 2018-05-02
Handbook Of Floating Point Arithmetic written by Jean-Michel Muller and has been published by Birkhäuser this book supported file pdf, txt, epub, kindle and other format this book has been release on 2018-05-02 with Mathematics categories.
Floating-point arithmetic is the most widely used way of implementing real-number arithmetic on modern computers. However, making such an arithmetic reliable and portable, yet fast, is a very difficult task. As a result, floating-point arithmetic is far from being exploited to its full potential. This handbook aims to provide a complete overview of modern floating-point arithmetic. So that the techniques presented can be put directly into practice in actual coding or design, they are illustrated, whenever possible, by a corresponding program. The handbook is designed for programmers of numerical applications, compiler designers, programmers of floating-point algorithms, designers of arithmetic operators, and more generally, students and researchers in numerical analysis who wish to better understand a tool used in their daily work and research.