Noise Speed And Power Tradeoffs In Pipelined Analog To Digital Converters
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Noise Speed And Power Tradeoffs In Pipelined Analog To Digital Converters
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Author : David William Cline
language : en
Publisher:
Release Date : 1995
Noise Speed And Power Tradeoffs In Pipelined Analog To Digital Converters written by David William Cline and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 1995 with categories.
Noise Speed And Power Tradeoffs In Piplined Analog To Digital Converters
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Author : David William Cline
language : en
Publisher:
Release Date : 1995
Noise Speed And Power Tradeoffs In Piplined Analog To Digital Converters written by David William Cline and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 1995 with Analog-to-digital converters categories.
Offset Reduction Techniques In High Speed Analog To Digital Converters
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Author : Pedro M. Figueiredo
language : en
Publisher: Springer Science & Business Media
Release Date : 2009-03-10
Offset Reduction Techniques In High Speed Analog To Digital Converters written by Pedro M. Figueiredo and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2009-03-10 with Technology & Engineering categories.
Offset Reduction Techniques in High-Speed Analog-to-Digital Converters analyzes, describes the design, and presents test results of Analog-to-Digital Converters (ADCs) employing the three main high-speed architectures: flash, two-step flash and folding and interpolation. The advantages and limitations of each one are reviewed, and the techniques employed to improve their performance are discussed.
High Speed Low Power Analog To Digital Converters
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Author : Shiuh-hua Chiang
language : en
Publisher:
Release Date : 2013
High Speed Low Power Analog To Digital Converters written by Shiuh-hua Chiang and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2013 with categories.
Analog-to-digital converters (ADCs) are widely used in communication systems to interface analog and digital circuits. While the speed, power, and area of digital circuits directly benefit from the decreasing channel length of CMOS devices, analog circuits suffer from reduced headroom, lower intrinsic gain, and higher device mismatch. Consequently, it has been increasingly difficult to design high-speed and low-power pipelined ADCs using conventional op amps. This work presents a pipelined ADC that employs novel "charge-steering" op amps to relax the trade-offs among speed, noise, and power consumption. Such op amps afford a fourfold increase in speed and a twofold reduction in noise for a given power consumption and voltage gain. Using a new clock gating technique, the ADC digitally calibrates the nonlinearity and gain error at full speed. A prototype realized in 65-nm CMOS technology achieves a resolution of 10 bits with a sampling rate of 800 MHz, a power consumption of 19 mW, an SNDR of 52.2 dB at Nyquist, and an FoM of 53 fJ/conversion-step. A new background calibration technique is also proposed to accommodate temperature and supply variations.
Low Power Design Approaches For Programmable Speed Pipelined Analog To Digital Converters
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Author : Anup Savla
language : en
Publisher:
Release Date : 2002
Low Power Design Approaches For Programmable Speed Pipelined Analog To Digital Converters written by Anup Savla and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2002 with categories.
High Speed A D Converters
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Author : Alfi Moscovici
language : en
Publisher: Springer Science & Business Media
Release Date : 2006-04-18
High Speed A D Converters written by Alfi Moscovici and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2006-04-18 with Technology & Engineering categories.
The Analog to Digital Converters represent one half of the link between the world we live in - analog - and the digital world of computers, which can handle the computations required in digital signal processing. These devices are mathematically very complex due to their nonlinear behavior and thus fairly difficult to analyze without the use of simulation tools. High Speed A/D Converters: Understanding Data Converters Through SPICE presents the subject from the practising engineer's point of view rather than from the academic's point of view. A practical approach is emphasized. High Speed A/D Converters: Understanding Data Converters Through SPICE is intended as a learning tool by providing building blocks that can be stacked on top of each other to build higher order systems. The book provides a guide to understanding the various topologies used in A/D converters by suggesting simple methods for the blocks used in an A/D converter. The converters discussed throughout the book constitute a class of devices called undersampled or Nyquist converters. The tools used in deriving the results presented are: TopSpice® by Penzar - a mixed mode SPICE simulator - version 5.90. The files included in Appendix A were written for this tool. However, most circuit files need only minor adjustments to be used on other SPICE simulators such as PSpice, Hspice, IS_Spice and Micro-Cap IV; Mathcad 2000 - Professional by Mathsoft. This tool is very useful in performing FFT analysis as well as drawing some of the graphs. Again, the mathcad files are included to help the user analyze the data. High Speed A/D Converters: Understanding Data Converters Through SPICE not only supplies the models for the A/D converters for SPICE program but also describes the physical reasons for the converter's performance.
Low Power Techniques For High Performance Pipelined Analog To Digital Converter
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Author : Byung-geun Lee
language : en
Publisher:
Release Date : 2007
Low Power Techniques For High Performance Pipelined Analog To Digital Converter written by Byung-geun Lee and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2007 with Operational amplifiers categories.
Low-power and small size analog to digital converters (ADCs) are the strategic building blocks in state of the art mobile wireless communication systems. Various techniques have been developed to reduce both power consumption and die area of the ADC. Among these, the opamp-sharing technique shows the most promise. In opamp-sharing, power and die area are saved by sharing one opamp between two successive pipeline stages. However, this technique suffers from the well-known memory effect drawback due to the absence of the reset phase that discharges the opamp's input parasitics. In this dissertation, this drawback is solved by introducing a discharge phase before the opamp is used for the pipeline stages without compromising speed and resolution of the ADC. Further power and area reduction is achieved by using a capacitor-sharing technique. This technique reduces the effective load capacitance of the opamp by reusing the charge on the feedback capacitor for the MDAC operation of the following stage, resulting in faster settling without increasing opamp power. The proposed low input-capacitance variable-gm opamp also helps to reduce the memory effect and improves the settling behavior of the stage output by increasing the bandwidth of the opamp while input parasitics of the opamp are kept small. The prototype designs of a 10-bit 50MSample/s pipelined ADC and a 14-bit 100MSample/s pipelined ADC implemented in 0.181m CMOS technology demonstrate the effectiveness of the proposed techniques. The first ADC achieves 56.2dB SNDR and 72.7dB SFDR for a Nyquist input at full sampling rate while consuming 12 mW from a 1.8-V supply. The FOM, defined as, [power/2[superscript ENOB]. Fs], is 0.46 pJ/step with Fin = 24.5MHz at 50MS/s. The second ADC achieves 72.4dB SNR and 88.5dB SFDR at 100MS/s with a 46MHz input and consumes 230mW from a 3V supply. The FOM of the second ADC is 0.69 pJ/step with Fin = 46MHz at 100MS/s.
Design Issues In High Speed Moderate Resolution Pipelined Analog To Digital Converters
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Author : Paul Stulik
language : en
Publisher:
Release Date : 1999
Design Issues In High Speed Moderate Resolution Pipelined Analog To Digital Converters written by Paul Stulik and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 1999 with Analog-to-digital converters categories.
Power Efficient Two Step Pipelined Analog To Digital Conversion
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Author : Ho-Young Lee
language : en
Publisher:
Release Date : 2011
Power Efficient Two Step Pipelined Analog To Digital Conversion written by Ho-Young Lee and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2011 with Pipelined ADCs categories.
Hand-held devices are among the most successful consumer electronics in modern society. Behind these successful devices, lies a key analog design technique that involves high-performance analog-to-digital conversion combined with very low power consumption. This dissertation presents two different approaches to achieving high power efficiency from a two-step pipelined architecture, which is generally known as one of the most power-consuming analog-to-digital converters. In the first approach, an analog feedback loop of a residue amplifier in a two-step pipelined analog-to-digital converter is reconfigured digitally using a single comparator and an R-2R digital-to-analog converter. This comparator-based structure can reduce power consumption of a conventional two-step pipelined analog-to-digital converter which consists of an opamp-based residue amplifier followed by a second- stage analog-to-digital converter. In addition, this dissertation includes circuit design techniques that provide a digital offset correction for the comparator-based two-step structure, binary-weighted switching for an R-2R digital-to-analog converter, and reference trimming for a flash analog-to-digital converter. A 10-b prototype analog-to-digital converter achieves an FOM of 121 fJ/conversion-step under 0.7-V supply. The second approach provides a way to achieve low power consumption for a high-resolution two-step pipelined analog-to-digital converter. An opamp is designed to consume optimized static power using a quarter-scaled residue gain together with minimized loading capacitance from the proposed second stage. A 14-b prototype analog-to-digital converter achieves an FOM of 31.3 fJ/conversion-step with an ENOB of 11.4 b, which is the lowest FOM in high-resolution analog-to-digital converters having greater than an ENOB of 10 b. Finally, the potential for further power reduction in a two-step pipelined analog-to-digital converter is discussed as a topic for future research.
Low Power Design Techniques For Pipelined Analog To Digital Converters
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Author : Paul Chuan-Wei Yu
language : en
Publisher:
Release Date : 1996
Low Power Design Techniques For Pipelined Analog To Digital Converters written by Paul Chuan-Wei Yu and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 1996 with categories.