Performance Analysis Of Timing Speculative Processors

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Performance Analysis Of Timing Speculative Processors

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Author : Omid Assare
language : en
Publisher:
Release Date : 2019

Performance Analysis Of Timing Speculative Processors written by Omid Assare and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2019 with categories.

Timing guardbands act as a barrier protecting conventional processors from circuit-level phenomena like timing errors. Timing-speculative (TS) processors replace these guardbands with timing error detection and recovery circuits to guarantee correct execution. For timing speculation to be effective, the performance and/or energy improvements gained from eliminating the guardbands must outweigh the costs of detecting and recovering from timing errors. The high costs and limited benefits that have been an obstacle to adoption of timing speculation in commercial designs have been steadily improving over the past decade. Likewise, recent advances in design of ultra-fast on-chip voltage regulators and all-digital phase locked loops with sub-nanosecond response times have increased the potential benefits by enabling more aggressive timing speculation schemes. This dissertation is motivated by another contributing factor limiting broader adoption of TS processors--complexity of their performance analysis. The absence of timing guardbands complicates timing analysis of TS processors as circuit and architecture, and their interdependence, must be considered simultaneously. We present a cross-layer performance analysis framework for TS processors that spans the system stack from circuit to application, including dynamic timing analysis tools at the level of gates, microarchitecture, and architecture, an instruction-level timing error model, and a statistical program error rate estimation methodology. We then use our framework to study the performance of a TS processor with an emphasis on characterizing the role of software. Our experiments show that the combination of running application and its input data can change the performance of a TS processor by as much as 25 percent, demonstrating that application-specific analysis is necessary for accurate evaluation of TS processors and should be used to inform design decisions and assess the suitability of applications for timing speculation. Performance of TS processors also relies on accurate prediction of the optimal operating point. Our experiments show that, in a typical case, the most commonly used policy achieves only a fraction of the potential gains of timing speculation. Inspired by our modeling of timing errors, the improved timing speculation strategies we propose in this dissertation can realize a more than 50 percent throughput improvement compared to a guardbanded design.

A Static Timing Analysis Method For Programs On High Performance Processors

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Author :
language : en
Publisher:
Release Date : 1999

A Static Timing Analysis Method For Programs On High Performance Processors written by and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 1999 with categories.

Synergistic Timing Speculation For Multi Threaded Programs

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Author : Atif Yasin
language : en
Publisher:
Release Date : 2016

Synergistic Timing Speculation For Multi Threaded Programs written by Atif Yasin and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2016 with categories.

Timing speculation is a promising approach to increase the processor performance and energy efficiency. Under timing speculation, an integrated circuit is allowed to operate at a speed faster than its slowest path|the critical path. It is based on the empirical observation, which is presented later in the thesis, that these critical path delays are rarely manifested during the program execution. Consequently, as long as the processor is equipped with an error detection and recovery mechanism, its performance can be increased and/or energy consumption reduced beyond that achievable by any other conventional operation. While many past works have dealt with timing speculation within a single core, in this work, a new direction is being uncovered | timing speculation for a multi-core processor executing a parallel, multi-threaded application. Through a rigorous cross-layered circuit architectural analysis, it is observed that during the execution of a multi-threaded program, there is a significant variation in circuit delay characteristics across different threads. Synergistic Timing Speculation (SynTS) is proposed to exploit this variation (heterogeneity) in path sensitization delays, to jointly optimize the energy and execution time of the many-core processor. In particular, SynTS uses a sampling based online error probability estimation technique, coupled with a polynomial time algorithm, to optimally determine the voltage, frequency and the amount of timing speculation for each thread. The experimental analysis is presented for three pipe stages, namely, Decode, SimpleALU and ComplexALU, with a reduction in Energy Delay Product by up to 26%, 25% and 7.5% respectively, compared to existing per-core timing speculation scheme. The analysis also embeds a case study for a General Purpose Graphics Processing Unit.

Providing Predictability For High End Embedded Systems

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Author :
language : en
Publisher:
Release Date : 2001

Providing Predictability For High End Embedded Systems written by and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2001 with categories.

Real-Time systems require logical and temporal correctness. Temporal correctness implies that each task running on the system has a deadline that needs to be met. To ensure that the deadlines are met, the scheduler of a real-time system needs information about the worst-case execution time (WCET) of each task. The task of determining the WCET of a task on a particular architecture is called timing analysis. Analysis techniques are broadly classified as static and dynamic. Dynamic timing analysis does not provide safe WCET bounds. Static analysis cannot be used on modern processors with features like out-of-order execution, dynamic branch prediction and speculative execution. Such features, while improving the average-case performance, induce counter-intuitive timing behavior known as timing anomalies. Hence, designers of hard real-time systems are forced to use architectures with simple in-order pipelines. This thesis develops and demonstrates the benefits of a hybrid timing analysis technique (combining static and dynamic analysis) on a processor simulator and on FPGA hardware to provide tight and safe WCET bounds. The technique makes the following contributions: * It enhances the realm of design for hard real-time systems by allowing the designers to use complex out-of-order architectures that exhibit timing anomalies. * It eliminates the need for complex prototyping of hardware for static timing analysis since the analysis can be done directly on the actual hardware. This has the added advantage of eliminating timing inaccuracies arising out of variations in manufacturing technology. * The method helps manufacturers to protect their Intellectual Property by eliminating the need to disclose architectural details for the purpose of static timing analysis.

Integrated Circuit And System Design Power And Timing Modeling Optimization And Simulation

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Author : Johan Vounckx
language : en
Publisher: Springer Science & Business Media
Release Date : 2006-09-08

Integrated Circuit And System Design Power And Timing Modeling Optimization And Simulation written by Johan Vounckx and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2006-09-08 with Computers categories.

This book constitutes the refereed proceedings of the 16th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2006. The book presents 41 revised full papers and 23 revised poster papers together with 4 key notes and 3 industrial abstracts. Topical sections include high-level design, power estimation and modeling memory and register files, low-power digital circuits, busses and interconnects, low-power techniques, applications and SoC design, modeling, and more.

International Symposium On System Synthesis

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Author :
language : en
Publisher:
Release Date : 2002

International Symposium On System Synthesis written by and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2002 with Computer-aided design categories.

Analysis Of A Combined Hardware Software Mechanism For Speculative Loads

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Author : Princeton University. Dept. of Computer Science
language : en
Publisher:
Release Date : 1994

Analysis Of A Combined Hardware Software Mechanism For Speculative Loads written by Princeton University. Dept. of Computer Science and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 1994 with Multiprocessors categories.

Abstract: "This paper describes a simple hardware mechanism and related compiler support for software-controlled speculative loads. The compiler issues speculative load instructions based on anticipated data references and the ability of the memory system to hide memory latency in high-performance processors. The architectural support for such a mechanism is simple and minimal, yet handles faults gracefully. We have simulated three speculative load mechanisms based on a MIPS processor and a detailed memory system. The results of scientific kernel loops indicate that speculative load techniques can hide memory latency effectively."

Optimal Power Performance Pipelining For Error Resilient Processors

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Author : Nicolas Zea
language : en
Publisher:
Release Date : 2010

Optimal Power Performance Pipelining For Error Resilient Processors written by Nicolas Zea and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2010 with categories.

Timing speculation has been proposed as a technique for maximizing energy efficiency of processors with minimal loss in performance. A typical implementation of timing speculation involves relaxing the timing constraints of a processor to a point where errors are possible but rare, and employing an error recovery mechanism to ensure correct functionality. This allows significant energy efficiency gains with a small recovery overhead. Previous work on timing speculation has either explored the benefits of customizing the design methodology for a particular error resilience mechanism or attempted to understand the benefits from error resilience for a particular resiliency mechanism. There is no work, to the best of our knowledge, that attempts to understand the benefits of co-optimizing microarchitecture and error resilience. In this thesis, we present the first study on co-optimizing a processor pipeline and an error resilience mechanism. We develop an analytical model that relates the benefits from error resiliency to the depth of the pipeline as well as its circuit structure. The model is then used to determine the optimal pipeline depth for different energy efficiency metrics for different error resilience overheads. Our results demonstrate that several interesting relationships exist between error resilience and pipeline structure. For example, we show that there are significant energy efficiency benefits to pipelining an architecture for an error resiliency mechanism versus error resiliency-agnostic pipelining. As another example, we show that benefits from error resiliency are greater for short pipelines than long pipelines. We also confirm that the benefits from error resiliency are higher when the circuit structure is such that the error rate increases slowly on reducing input voltage versus a circuit optimized for power where a slack wall exists at the nominal operating point. We quantify the difference in benefits from error resiliency for irregular versus regular workloads and show that benefits from error resiliency are higher for irregular workloads. Finally, we discuss the relationship between frequency and voltage-based timing speculation schemes, and draw conclusions about when is best to employ each. Our analytical results were validated using a cycle-accurate simulation-based model.

Timing Analysis Of High Performance Integrated Circuits

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Author : Chirayu S. Amin
language : en
Publisher:
Release Date : 2005

Timing Analysis Of High Performance Integrated Circuits written by Chirayu S. Amin and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2005 with categories.

A novel waveform model for improving the accuracy of gate delay prediction in static timing analysis has been developed. Moreover, a full methodology on modeling complex circuits such as unbuffered latches for timing analysis has been developed. Since variations in process, environment, and temperature have become very important, a simple path-based statistical static timing analysis algorithm has also been proposed. The algorithm models timing variations accurately for latest high-performance microprocessors.

Detection Of Intrusions And Malware And Vulnerability Assessment

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Author : Leyla Bilge
language : en
Publisher: Springer Nature
Release Date : 2021-07-09

Detection Of Intrusions And Malware And Vulnerability Assessment written by Leyla Bilge and has been published by Springer Nature this book supported file pdf, txt, epub, kindle and other format this book has been release on 2021-07-09 with Computers categories.

This book constitutes the proceedings of the 18th International Conference on Detection of Intrusions and Malware, and Vulnerability Assessment, DIMVA 2021, held virtually in July 2021. The 18 full papers and 1 short paper presented in this volume were carefully reviewed and selected from 65 submissions. DIMVA serves as a premier forum for advancing the state of the art in intrusion detection, malware detection, and vulnerability assessment. Each year, DIMVA brings together international experts from academia, industry, and government to present and discuss novel research in these areas. Chapter “SPECULARIZER: Detecting Speculative Execution Attacks via Performance Tracing” is available open access under a Creative Commons Attribution 4.0 International License via link.springer.com.