Pipelined Analog To Digital Conversion Using Class Ab Amplifiers
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Pipelined Analog To Digital Conversion Using Class Ab Amplifiers
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Author : Kyung Ryun Kim
language : en
Publisher: Stanford University
Release Date : 2010
Pipelined Analog To Digital Conversion Using Class Ab Amplifiers written by Kyung Ryun Kim and has been published by Stanford University this book supported file pdf, txt, epub, kindle and other format this book has been release on 2010 with categories.
In high-performance pipelined analog-to-digital converters (ADCs), the residue amplifiers dissipate the majority of the overall converter power. Therefore, finding alternatives to the relatively inefficient, conventional class-A circuit realization is an active area of research. One option for improvement is to employ class-AB amplifiers, which can, in principle, provide large drive currents on demand and improve the efficiency of residue amplification. Unfortunately, due to the simultaneous demand for high speed and high gain in pipelined ADCs, the improvements seen in class-AB designs have so far been limited. This dissertation presents the design of an efficient class-AB amplification scheme based on a pseudo-differential, single-stage and cascode-free architecture. Nonlinear errors due to finite DC gain are addressed using a deterministic digital background calibration that measures the circuit imperfections in time intervals between normal conversion cycles of the ADC. As a proof of concept, a 12-bit 30-MS/s pipelined ADC was realized using class-AB amplifiers with the proposed digital calibration. The prototype ADC occupies an active area of 0.36 mm2 in 90-nm CMOS. It dissipates 2.95 mW from a 1.2-V supply and achieves an SNDR of 64.5 dB for inputs near the Nyquist frequency. The corresponding figure of merit is 72 fJ/conversion-step.
Pipelined Analog To Digital Conversion Using Class Ab Amplifiers
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Author : Kyung Ryun Kim
language : en
Publisher:
Release Date : 2010
Pipelined Analog To Digital Conversion Using Class Ab Amplifiers written by Kyung Ryun Kim and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2010 with categories.
In high-performance pipelined analog-to-digital converters (ADCs), the residue amplifiers dissipate the majority of the overall converter power. Therefore, finding alternatives to the relatively inefficient, conventional class-A circuit realization is an active area of research. One option for improvement is to employ class-AB amplifiers, which can, in principle, provide large drive currents on demand and improve the efficiency of residue amplification. Unfortunately, due to the simultaneous demand for high speed and high gain in pipelined ADCs, the improvements seen in class-AB designs have so far been limited. This dissertation presents the design of an efficient class-AB amplification scheme based on a pseudo-differential, single-stage and cascode-free architecture. Nonlinear errors due to finite DC gain are addressed using a deterministic digital background calibration that measures the circuit imperfections in time intervals between normal conversion cycles of the ADC. As a proof of concept, a 12-bit 30-MS/s pipelined ADC was realized using class-AB amplifiers with the proposed digital calibration. The prototype ADC occupies an active area of 0.36 mm2 in 90-nm CMOS. It dissipates 2.95 mW from a 1.2-V supply and achieves an SNDR of 64.5 dB for inputs near the Nyquist frequency. The corresponding figure of merit is 72 fJ/conversion-step.
Reference Free Cmos Pipeline Analog To Digital Converters
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Author : Michael Figueiredo
language : en
Publisher: Springer Science & Business Media
Release Date : 2012-08-24
Reference Free Cmos Pipeline Analog To Digital Converters written by Michael Figueiredo and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2012-08-24 with Technology & Engineering categories.
This book shows that digitally assisted analog to digital converters are not the only way to cope with poor analog performance caused by technology scaling. It describes various analog design techniques that enhance the area and power efficiency without employing any type of digital calibration circuitry. These techniques consist of self-biasing for PVT enhancement, inverter-based design for improved speed/power ratio, gain-of-two obtained by voltage sum instead of charge redistribution, and current-mode reference shifting instead of voltage reference shifting. Together, these techniques allow enhancing the area and power efficiency of the main building blocks of a multiplying digital-to-analog converter (MDAC) based stage, namely, the flash quantizer, the amplifier, and the switched capacitor network of the MDAC. Complementing the theoretical analyses of the various techniques, a power efficient operational transconductance amplifier is implemented and experimentally characterized. Furthermore, a medium-low resolution reference-free high-speed time-interleaved pipeline ADC employing all mentioned design techniques and circuits is presented, implemented and experimentally characterized. This ADC is said to be reference-free because it precludes any reference voltage, therefore saving power and area, as reference circuits are not necessary. Experimental results demonstrate the potential of the techniques which enabled the implementation of area and power efficient circuits.
Power Efficient Two Step Pipelined Analog To Digital Conversion
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Author : Ho-Young Lee
language : en
Publisher:
Release Date : 2011
Power Efficient Two Step Pipelined Analog To Digital Conversion written by Ho-Young Lee and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2011 with Pipelined ADCs categories.
Hand-held devices are among the most successful consumer electronics in modern society. Behind these successful devices, lies a key analog design technique that involves high-performance analog-to-digital conversion combined with very low power consumption. This dissertation presents two different approaches to achieving high power efficiency from a two-step pipelined architecture, which is generally known as one of the most power-consuming analog-to-digital converters. In the first approach, an analog feedback loop of a residue amplifier in a two-step pipelined analog-to-digital converter is reconfigured digitally using a single comparator and an R-2R digital-to-analog converter. This comparator-based structure can reduce power consumption of a conventional two-step pipelined analog-to-digital converter which consists of an opamp-based residue amplifier followed by a second- stage analog-to-digital converter. In addition, this dissertation includes circuit design techniques that provide a digital offset correction for the comparator-based two-step structure, binary-weighted switching for an R-2R digital-to-analog converter, and reference trimming for a flash analog-to-digital converter. A 10-b prototype analog-to-digital converter achieves an FOM of 121 fJ/conversion-step under 0.7-V supply. The second approach provides a way to achieve low power consumption for a high-resolution two-step pipelined analog-to-digital converter. An opamp is designed to consume optimized static power using a quarter-scaled residue gain together with minimized loading capacitance from the proposed second stage. A 14-b prototype analog-to-digital converter achieves an FOM of 31.3 fJ/conversion-step with an ENOB of 11.4 b, which is the lowest FOM in high-resolution analog-to-digital converters having greater than an ENOB of 10 b. Finally, the potential for further power reduction in a two-step pipelined analog-to-digital converter is discussed as a topic for future research.
A High Speed Pipelined Analog To Digital Converter Using Wide Band Sample And Hold Amplifier
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Author : 邵姿菁
language : en
Publisher:
Release Date : 2009
A High Speed Pipelined Analog To Digital Converter Using Wide Band Sample And Hold Amplifier written by 邵姿菁 and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2009 with categories.
Analog Circuit Design
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Author : Michiel Steyaert
language : en
Publisher: Springer Science & Business Media
Release Date : 2011-09-15
Analog Circuit Design written by Michiel Steyaert and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2011-09-15 with Technology & Engineering categories.
Analog Circuit Design contains the contribution of 18 tutorials of the 20th workshop on Advances in Analog Circuit Design. Each part discusses a specific to-date topic on new and valuable design ideas in the area of analog circuit design. Each part is presented by six experts in that field and state of the art information is shared and overviewed. This book is number 20 in this successful series of Analog Circuit Design, providing valuable information and excellent overviews of: Topic 1 : Low Voltage Low Power, chairman: Andrea Baschirotto Topic 2 : Short Range Wireless Front-Ends, chairman: Arthur van Roermund Topic 3 : Power Management and DC-DC, chairman : Michiel Steyaert. Analog Circuit Design is an essential reference source for analog circuit designers and researchers wishing to keep abreast with the latest development in the field. The tutorial coverage also makes it suitable for use in an advanced design course.
Pipelined Analog To Digital Conversion Using Low Precision Analog Building Blocks With Digital Calibration
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Author : Dong Wang
language : en
Publisher:
Release Date : 2012
Pipelined Analog To Digital Conversion Using Low Precision Analog Building Blocks With Digital Calibration written by Dong Wang and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2012 with categories.
The pipelined analog-to-digital converter (ADC) is widely used in high-speed, high-resolution analog-to-digital conversion applications. The advantages of using the pipelined architecture include low power and small area. One drawback of the pipelined architecture is that when used for high-resolution applications, the first few stages of the pipeline require high linearity and low noise. With scaling of CMOS technologies, high-precision analog building blocks become more difficult to design, while the cost of digital circuits shrinks in terms of both area and power. One approach to designing a pipelined ADC in modern CMOS technologies is to shift design complexity from the analog domain to the digital domain. In particular, a pipelined ADC can be designed with low-precision analog building blocks and the resulting non-idealities can be corrected digitally. To demonstrate the feasibility of shifting design complexity from the analog domain to the digital domain, a 12-bit 40 MS/s pipelined ADC prototype is implemented with a few different low-precision analog building blocks and the resulting non-idealities are all corrected digitally. To begin, an integrator-based residue amplifier is implemented in the first stage of the pipeline. In addition, outputs of the traditional residue amplifiers used in later stages are sampled before settling. Finally, to reduce coupling between stages through shared reference voltages, three separate reference voltage generators are used in the pipeline. The nonlinearities arising from the integrator-based residue amplifier, from the early sampling of the residue-amplifier output and from the separate reference generators are all corrected digitally. Overall, calibration improves SFDR from 50.8 dB to 92.4 dB and improves SNDR from 42.7 dB to 68.8 dB. The prototype ADC's power dissipation is 140 mW.
Video Rate Analog To Digital Conversion Using Pipelined Architectures
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Author : Stephen Henry Lewis
language : en
Publisher:
Release Date : 1987
Video Rate Analog To Digital Conversion Using Pipelined Architectures written by Stephen Henry Lewis and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 1987 with categories.
Analog Circuit Design
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Author : Johan Huijsing
language : en
Publisher: Springer Science & Business Media
Release Date : 2013-04-17
Analog Circuit Design written by Johan Huijsing and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2013-04-17 with Computers categories.
Many interesting design trends are shown by the six papers on operational amplifiers (Op Amps). Firstly. there is the line of stand-alone Op Amps using a bipolar IC technology which combines high-frequency and high voltage. This line is represented in papers by Bill Gross and Derek Bowers. Bill Gross shows an improved high-frequency compensation technique of a high quality three stage Op Amp. Derek Bowers improves the gain and frequency behaviour of the stages of a two-stage Op Amp. Both papers also present trends in current-mode feedback Op Amps. Low-voltage bipolar Op Amp design is presented by leroen Fonderie. He shows how multipath nested Miller compensation can be applied to turn rail-to-rail input and output stages into high quality low-voltage Op Amps. Two papers on CMOS Op Amps by Michael Steyaert and Klaas Bult show how high speed and high gain VLSI building blocks can be realised. Without departing from a single-stage OT A structure with a folded cascode output, a thorough high frequency design technique and a gain-boosting technique contributed to the high-speed and the high-gain achieved with these Op Amps. . Finally. Rinaldo Castello shows us how to provide output power with CMOS buffer amplifiers. The combination of class A and AB stages in a multipath nested Miller structure provides the required linearity and bandwidth.
Analog Circuit Design
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Author : Rudy J. van de Plassche
language : en
Publisher: Springer Science & Business Media
Release Date : 2013-06-29
Analog Circuit Design written by Rudy J. van de Plassche and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2013-06-29 with Technology & Engineering categories.
The realization of signal sampling and quantization at high sample rates with low power dissipation is an important goal in many applications, includ ing portable video devices such as camcorders, personal communication devices such as wireless LAN transceivers, in the read channels of magnetic storage devices using digital data detection, and many others. This paper describes architecture and circuit approaches for the design of high-speed, low-power pipeline analog-to-digital converters in CMOS. Here the term high speed is taken to imply sampling rates above 1 Mhz. In the first section the dif ferent conversion techniques applicable in this range of sample rates is dis cussed. Following that the particular problems associated with power minimization in video-rate pipeline ADCs is discussed. These include optimi zation of capacitor sizes, design of low-voltage transmission gates, and opti mization of switched capacitor gain blocks and operational amplifiers for minimum power dissipation. As an example of the application of these tech niques, the design of a power-optimized lO-bit pipeline AID converter (ADC) that achieves =1. 67 mW per MS/s of sampling rate from 1 MS/s to 20 MS/s is described. 2. Techniques for CMOS Video-Rate AID Conversion Analog-to-digital conversion techniques can be categorized in many ways. One convenient means of comparing techniques is to examine the number of "analog clock cycles" required to produce one effective output sample of the signal being quantized.