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Techniques For Low Power High Performance Analog To Digital Converters


Techniques For Low Power High Performance Analog To Digital Converters
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Low Power High Resolution Analog To Digital Converters


Low Power High Resolution Analog To Digital Converters
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Author : Amir Zjajo
language : en
Publisher: Springer Science & Business Media
Release Date : 2010-10-29

Low Power High Resolution Analog To Digital Converters written by Amir Zjajo and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2010-10-29 with Technology & Engineering categories.


With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. This has recently generated a great demand for low-power, low-voltage A/D converters that can be realized in a mainstream deep-submicron CMOS technology. However, the discrepancies between lithography wavelengths and circuit feature sizes are increasing. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. The inherent randomness of materials used in fabrication at nanoscopic scales means that performance will be increasingly variable, not only from die-to-die but also within each individual die. Parametric variability will be compounded by degradation in nanoscale integrated circuits resulting in instability of parameters over time, eventually leading to the development of faults. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods. In an attempt to address these issues, Low-Power High-Resolution Analog-to-Digital Converters specifically focus on: i) improving the power efficiency for the high-speed, and low spurious spectral A/D conversion performance by exploring the potential of low-voltage analog design and calibration techniques, respectively, and ii) development of circuit techniques and algorithms to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover errors continuously. The feasibility of the described methods has been verified by measurements from the silicon prototypes fabricated in standard 180nm, 90nm and 65nm CMOS technology.



High Resolution And High Speed Integrated Cmos Ad Converters For Low Power Applications


High Resolution And High Speed Integrated Cmos Ad Converters For Low Power Applications
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Author : Weitao Li
language : en
Publisher: Springer
Release Date : 2017-08-01

High Resolution And High Speed Integrated Cmos Ad Converters For Low Power Applications written by Weitao Li and has been published by Springer this book supported file pdf, txt, epub, kindle and other format this book has been release on 2017-08-01 with Technology & Engineering categories.


This book is a step-by-step tutorial on how to design a low-power, high-resolution (not less than 12 bit), and high-speed (not less than 200 MSps) integrated CMOS analog-to-digital (AD) converter, to respond to the challenge from the rapid growth of IoT. The discussion includes design techniques on both the system level and the circuit block level. In the architecture level, the power-efficient pipelined AD converter, the hybrid AD converter and the time-interleaved AD converter are described. In the circuit block level, the reference voltage buffer, the opamp, the comparator, and the calibration are presented. Readers designing low-power and high-performance AD converters won’t want to miss this invaluable reference. Provides an in-depth introduction to the newest design techniques for the power-efficient, high-resolution (not less than 12 bit), and high-speed (not less than 200 MSps) AD converter; Presents three types of power-efficient architectures of the high-resolution and high-speed AD converter; Discusses the relevant circuit blocks (i.e., the reference voltage buffer, the opamp, and the comparator) in two aspects, relaxing the requirements and improving the performance.



Generalized Low Voltage Circuit Techniques For Very High Speed Time Interleaved Analog To Digital Converters


Generalized Low Voltage Circuit Techniques For Very High Speed Time Interleaved Analog To Digital Converters
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Author : Sai-Weng Sin
language : en
Publisher: Springer Science & Business Media
Release Date : 2010-09-29

Generalized Low Voltage Circuit Techniques For Very High Speed Time Interleaved Analog To Digital Converters written by Sai-Weng Sin and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2010-09-29 with Technology & Engineering categories.


Analog-to-Digital Converters (ADCs) play an important role in most modern signal processing and wireless communication systems where extensive signal manipulation is necessary to be performed by complicated digital signal processing (DSP) circuitry. This trend also creates the possibility of fabricating all functional blocks of a system in a single chip (System On Chip - SoC), with great reductions in cost, chip area and power consumption. However, this tendency places an increasing challenge, in terms of speed, resolution, power consumption, and noise performance, in the design of the front-end ADC which is usually the bottleneck of the whole system, especially under the unavoidable low supply-voltage imposed by technology scaling, as well as the requirement of battery operated portable devices. Generalized Low-Voltage Circuit Techniques for Very High-Speed Time-Interleaved Analog-to-Digital Converters will present new techniques tailored for low-voltage and high-speed Switched-Capacitor (SC) ADC with various design-specific considerations.



Offset Reduction Techniques In High Speed Analog To Digital Converters


Offset Reduction Techniques In High Speed Analog To Digital Converters
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Author : Pedro M. Figueiredo
language : en
Publisher: Springer Science & Business Media
Release Date : 2009-03-10

Offset Reduction Techniques In High Speed Analog To Digital Converters written by Pedro M. Figueiredo and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2009-03-10 with Technology & Engineering categories.


Offset Reduction Techniques in High-Speed Analog-to-Digital Converters analyzes, describes the design, and presents test results of Analog-to-Digital Converters (ADCs) employing the three main high-speed architectures: flash, two-step flash and folding and interpolation. The advantages and limitations of each one are reviewed, and the techniques employed to improve their performance are discussed.



Design Techniques For Low Power High Speed Successive Approximation Analog To Digital Converters


Design Techniques For Low Power High Speed Successive Approximation Analog To Digital Converters
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Author : Jiaming Lin
language : en
Publisher:
Release Date : 2013

Design Techniques For Low Power High Speed Successive Approximation Analog To Digital Converters written by Jiaming Lin and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2013 with Successive approximation analog-to-digital converters categories.


This dissertation presents two high-speed pipeline successive approximation analog-to-digital converters (SAR ADCs). Capacitive DACs and resistive DACs are utilized in these two pipeline SAR ADCs, respectively. The pipeline SAR ADC with capacitive DACs can save 50% switching power compared with other time-interleaved SAR ADCs since the total capacitance of the DACs in this ADC is more than 50% less than the conventional time-interleave ones. Several switching techniques are implemented to alleviate the impact from the parasitic capacitance and improve the performance. The pipeline SAR ADC with resistive DACs overcomes the influence from the parasitic capacitance with negligible static power consumption on the resistive DACs. Also, the complicated switching techniques can be avoided to simplify the timing logic. To verify the above two architectures, two chips were designed and fabricated in 40nm CMOS process. Finally, a new architecture of multi-step capacitive-splitting SAR ADC is proposed for low power applications. By using two identical capacitor-splitting capacitor arrays, the switching power and capacitor area can be reduced significantly.



Analog Circuit Design


Analog Circuit Design
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Author : Rudy J. van de Plassche
language : en
Publisher: Springer Science & Business Media
Release Date : 2013-06-29

Analog Circuit Design written by Rudy J. van de Plassche and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2013-06-29 with Technology & Engineering categories.


The realization of signal sampling and quantization at high sample rates with low power dissipation is an important goal in many applications, includ ing portable video devices such as camcorders, personal communication devices such as wireless LAN transceivers, in the read channels of magnetic storage devices using digital data detection, and many others. This paper describes architecture and circuit approaches for the design of high-speed, low-power pipeline analog-to-digital converters in CMOS. Here the term high speed is taken to imply sampling rates above 1 Mhz. In the first section the dif ferent conversion techniques applicable in this range of sample rates is dis cussed. Following that the particular problems associated with power minimization in video-rate pipeline ADCs is discussed. These include optimi zation of capacitor sizes, design of low-voltage transmission gates, and opti mization of switched capacitor gain blocks and operational amplifiers for minimum power dissipation. As an example of the application of these tech niques, the design of a power-optimized lO-bit pipeline AID converter (ADC) that achieves =1. 67 mW per MS/s of sampling rate from 1 MS/s to 20 MS/s is described. 2. Techniques for CMOS Video-Rate AID Conversion Analog-to-digital conversion techniques can be categorized in many ways. One convenient means of comparing techniques is to examine the number of "analog clock cycles" required to produce one effective output sample of the signal being quantized.



Analog Circuit Design


Analog Circuit Design
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Author : Rudy J. van de Plassche
language : en
Publisher: Springer Science & Business Media
Release Date : 2000-09-30

Analog Circuit Design written by Rudy J. van de Plassche and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2000-09-30 with Computers categories.


This volume of Analog Circuit Design concentrates on 3 topics: High-Speed Analog-to-Digital Converters, Mixed Signal Design and PLLs and Synthesizers. The book comprises 6 papers on each topic written by internationally recognized experts. These papers have a tutorial nature aimed at improving the design of analog circuits. The book is divided into 3 parts: Part I, High-Speed Analog-to-Digital Converters, describes the latest techniques for producing analog-to-digital converters for applications in disk drives, radio circuits, XDSL and super HiFi audio conversion. Converters having resolutions between 7-bit and 12-bit using CMOS techniques are presented. A 13-bit bandpass sigma-delta modulator for IF signal conversion concludes this part. Part II, Mixed Signal Design, presents papers that detail nearly all known techniques and design issues for mixed signal circuits using CAD tools. Applications for telecom, sigma-delta converters, systems-on-a-chip and RF circuitry are described. Part III, PLLs and Synthesizers, illustrates up-to-date techniques for combination of inductors on a CMOS chip together with PLL techniques to obtain low-noise frequency synthesizers for telecom applications. Special attention is paid to fractional N synthesizers using sigma-delta algorithms. Analog Circuit Design is an essential reference source for analog design engineers and researchers wishing to keep abreast with the latest developments in the field. The tutorial nature of the contributions also makes it suitable for use in an advanced design course.



Low Power Techniques For High Performance Pipelined Analog To Digital Converter


Low Power Techniques For High Performance Pipelined Analog To Digital Converter
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Author : Byung-geun Lee
language : en
Publisher:
Release Date : 2007

Low Power Techniques For High Performance Pipelined Analog To Digital Converter written by Byung-geun Lee and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2007 with Operational amplifiers categories.


Low-power and small size analog to digital converters (ADCs) are the strategic building blocks in state of the art mobile wireless communication systems. Various techniques have been developed to reduce both power consumption and die area of the ADC. Among these, the opamp-sharing technique shows the most promise. In opamp-sharing, power and die area are saved by sharing one opamp between two successive pipeline stages. However, this technique suffers from the well-known memory effect drawback due to the absence of the reset phase that discharges the opamp's input parasitics. In this dissertation, this drawback is solved by introducing a discharge phase before the opamp is used for the pipeline stages without compromising speed and resolution of the ADC. Further power and area reduction is achieved by using a capacitor-sharing technique. This technique reduces the effective load capacitance of the opamp by reusing the charge on the feedback capacitor for the MDAC operation of the following stage, resulting in faster settling without increasing opamp power. The proposed low input-capacitance variable-gm opamp also helps to reduce the memory effect and improves the settling behavior of the stage output by increasing the bandwidth of the opamp while input parasitics of the opamp are kept small. The prototype designs of a 10-bit 50MSample/s pipelined ADC and a 14-bit 100MSample/s pipelined ADC implemented in 0.181m CMOS technology demonstrate the effectiveness of the proposed techniques. The first ADC achieves 56.2dB SNDR and 72.7dB SFDR for a Nyquist input at full sampling rate while consuming 12 mW from a 1.8-V supply. The FOM, defined as, [power/2[superscript ENOB]. Fs], is 0.46 pJ/step with Fin = 24.5MHz at 50MS/s. The second ADC achieves 72.4dB SNR and 88.5dB SFDR at 100MS/s with a 46MHz input and consumes 230mW from a 3V supply. The FOM of the second ADC is 0.69 pJ/step with Fin = 46MHz at 100MS/s.



Reference Free Cmos Pipeline Analog To Digital Converters


Reference Free Cmos Pipeline Analog To Digital Converters
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Author : Michael Figueiredo
language : en
Publisher: Springer Science & Business Media
Release Date : 2012-08-24

Reference Free Cmos Pipeline Analog To Digital Converters written by Michael Figueiredo and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2012-08-24 with Technology & Engineering categories.


This book shows that digitally assisted analog to digital converters are not the only way to cope with poor analog performance caused by technology scaling. It describes various analog design techniques that enhance the area and power efficiency without employing any type of digital calibration circuitry. These techniques consist of self-biasing for PVT enhancement, inverter-based design for improved speed/power ratio, gain-of-two obtained by voltage sum instead of charge redistribution, and current-mode reference shifting instead of voltage reference shifting. Together, these techniques allow enhancing the area and power efficiency of the main building blocks of a multiplying digital-to-analog converter (MDAC) based stage, namely, the flash quantizer, the amplifier, and the switched capacitor network of the MDAC. Complementing the theoretical analyses of the various techniques, a power efficient operational transconductance amplifier is implemented and experimentally characterized. Furthermore, a medium-low resolution reference-free high-speed time-interleaved pipeline ADC employing all mentioned design techniques and circuits is presented, implemented and experimentally characterized. This ADC is said to be reference-free because it precludes any reference voltage, therefore saving power and area, as reference circuits are not necessary. Experimental results demonstrate the potential of the techniques which enabled the implementation of area and power efficient circuits.



Techniques For Low Power High Performance Analog To Digital Converters


Techniques For Low Power High Performance Analog To Digital Converters
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Author : Sunghyuk Lee
language : en
Publisher:
Release Date : 2014

Techniques For Low Power High Performance Analog To Digital Converters written by Sunghyuk Lee and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2014 with categories.


Analog-to-digital converters (ADCs) are essential building blocks in many electronic systems which require digital signal processing and storage of analog signals. Traditionally, ADCs are considered a power hungry circuit. This thesis investigates ADC design techniques to achieve high-performance with low power consumption. Two designs are demonstrated. The first design is a voltage scalable zero-crossing based pipelined ADC. The zero-crossing based circuit technique is modified and optimized to improve the limited ADC resolution in nano-scaled CMOS technology. The proposed unidirectional charge transfer scheme allows faster and more energy efficient operation by eliminating unnecessary charging and discharging of the capacitors. Furthermore, the reduced transient disturbance at the beginning of the fine charge transfer phase improves the accuracy of operation. Power supply scaling enhances power efficiency at low sampling rates much like in digital circuits and widens the conversion frequency range where the ADC operates with highest efficiency. The second design is a high speed time-interleaved (TI) SAR ADC with background timing-skew calibration. A time-interleaved structure is employed to improve the effective sampling rate without sacrificing energy efficiency. SAR ADCs are used for each channel to make good use of device scaling. The proposed ADC architecture incorporates a flash ADC operating at the full sampling rate of the TI ADC. The flash ADC output is multiplexed to resolve MSBs of the SAR channels. Because the full-speed flash ADC does not suffer from timing-skew errors, the flash ADC output is also used as the timing reference to estimate the timing-skew of the SAR ADCs.