Accuracy Enhancement Techniques In Low Voltage High Speed Pipelined Adc Design

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Accuracy Enhancement Techniques In Low Voltage High Speed Pipelined Adc Design

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Author : Jipeng Li
language : en
Publisher:
Release Date : 2003

Accuracy Enhancement Techniques In Low Voltage High Speed Pipelined Adc Design written by Jipeng Li and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2003 with Analog-to-digital converters categories.

Pipelined Adc Design And Enhancement Techniques

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Author : Imran Ahmed
language : en
Publisher: Springer Science & Business Media
Release Date : 2010-03-10

Pipelined Adc Design And Enhancement Techniques written by Imran Ahmed and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2010-03-10 with Technology & Engineering categories.

Pipelined ADCs have seen phenomenal improvements in performance over the last few years. As such, when designing a pipelined ADC a clear understanding of the design tradeoffs, and state of the art techniques is required to implement today's high performance low power ADCs.

Circuit Techniques For Low Voltage And High Speed A D Converters

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Author : Mikko E. Waltari
language : en
Publisher: Springer Science & Business Media
Release Date : 2005-12-30

Circuit Techniques For Low Voltage And High Speed A D Converters written by Mikko E. Waltari and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2005-12-30 with Technology & Engineering categories.

This useful monograph presents a total of seven prototypes: two double-sampled S/H circuits, a time-interleaved ADC, an IF-sampling self-calibrated pipelined ADC, a current steering DAC with a deglitcher, and two pipelined ADCs employing the SO techniques.

Reference Free Cmos Pipeline Analog To Digital Converters

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Author : Michael Figueiredo
language : en
Publisher: Springer Science & Business Media
Release Date : 2012-08-24

Reference Free Cmos Pipeline Analog To Digital Converters written by Michael Figueiredo and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2012-08-24 with Technology & Engineering categories.

This book shows that digitally assisted analog to digital converters are not the only way to cope with poor analog performance caused by technology scaling. It describes various analog design techniques that enhance the area and power efficiency without employing any type of digital calibration circuitry. These techniques consist of self-biasing for PVT enhancement, inverter-based design for improved speed/power ratio, gain-of-two obtained by voltage sum instead of charge redistribution, and current-mode reference shifting instead of voltage reference shifting. Together, these techniques allow enhancing the area and power efficiency of the main building blocks of a multiplying digital-to-analog converter (MDAC) based stage, namely, the flash quantizer, the amplifier, and the switched capacitor network of the MDAC. Complementing the theoretical analyses of the various techniques, a power efficient operational transconductance amplifier is implemented and experimentally characterized. Furthermore, a medium-low resolution reference-free high-speed time-interleaved pipeline ADC employing all mentioned design techniques and circuits is presented, implemented and experimentally characterized. This ADC is said to be reference-free because it precludes any reference voltage, therefore saving power and area, as reference circuits are not necessary. Experimental results demonstrate the potential of the techniques which enabled the implementation of area and power efficient circuits.

Systematic Design For Optimisation Of Pipelined Adcs

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Author : João Goes
language : en
Publisher: Springer Science & Business Media
Release Date : 2006-04-18

Systematic Design For Optimisation Of Pipelined Adcs written by João Goes and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2006-04-18 with Technology & Engineering categories.

This excellent reference proposes and develops new strategies, methodologies and tools for designing low-power and low-area CMOS pipelined A/D converters. The task is tackled by following a scientifically-consistent approach. The book may also be used as a text for advanced reading on the subject.

Power Efficient High Speed Parallel Sampling Adcs For Broadband Multi Carrier Systems

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Author : Yu Lin
language : en
Publisher: Springer
Release Date : 2015-05-07

Power Efficient High Speed Parallel Sampling Adcs For Broadband Multi Carrier Systems written by Yu Lin and has been published by Springer this book supported file pdf, txt, epub, kindle and other format this book has been release on 2015-05-07 with Technology & Engineering categories.

This book addresses the challenges of designing high performance analog-to-digital converters (ADCs) based on the “smart data converters” concept, which implies context awareness, on-chip intelligence and adaptation. Readers will learn to exploit various information either a-priori or a-posteriori (obtained from devices, signals, applications or the ambient situations, etc.) for circuit and architecture optimization during the design phase or adaptation during operation, to enhance data converters performance, flexibility, robustness and power-efficiency. The authors focus on exploiting the a-priori knowledge of the system/application to develop enhancement techniques for ADCs, with particular emphasis on improving the power efficiency of high-speed and high-resolution ADCs for broadband multi-carrier systems.

Low Power Design Techniques For High Speed Pipelined Adcs

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Author : Naga Sasidhar Lingam
language : en
Publisher:
Release Date : 2009

Low Power Design Techniques For High Speed Pipelined Adcs written by Naga Sasidhar Lingam and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2009 with Low voltage integrated circuits categories.

Real world is analog but the processing of signals can best be done in digital domain. So the need for Analog to Digital Converters (ADCs) is ever rising as more and more applications set in. With the advent of mobile technology, power in electronic equipment is being driven down to get more battery life. Because of their ubiquitous nature, ADCs are prime blocks in the signal chain in which power is intended to be reduced. In this thesis, four techniques to reduce power in high speed pipelined ADCs have been proposed. The first is a capacitor and opamp sharing technique that reduces the load on the first stage opamp by three fold. The second is a capacitor reset technique that aids removing the sample and hold block to reduce power. The third is a modified MDAC which can take rail-to-rail input swing to get an extra bit thus getting rid of a power hungry opamp. The fourth is a hybrid architecture which makes use of an asynchronous SAR ADC as the backend of a pipelined ADC to save power. Measurement and simulation results that prove the efficiency of the proposed techniques are presented.

Techniques For Low Power High Performance Analog To Digital Converters

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Author : Sunghyuk Lee
language : en
Publisher:
Release Date : 2014

Techniques For Low Power High Performance Analog To Digital Converters written by Sunghyuk Lee and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2014 with categories.

Analog-to-digital converters (ADCs) are essential building blocks in many electronic systems which require digital signal processing and storage of analog signals. Traditionally, ADCs are considered a power hungry circuit. This thesis investigates ADC design techniques to achieve high-performance with low power consumption. Two designs are demonstrated. The first design is a voltage scalable zero-crossing based pipelined ADC. The zero-crossing based circuit technique is modified and optimized to improve the limited ADC resolution in nano-scaled CMOS technology. The proposed unidirectional charge transfer scheme allows faster and more energy efficient operation by eliminating unnecessary charging and discharging of the capacitors. Furthermore, the reduced transient disturbance at the beginning of the fine charge transfer phase improves the accuracy of operation. Power supply scaling enhances power efficiency at low sampling rates much like in digital circuits and widens the conversion frequency range where the ADC operates with highest efficiency. The second design is a high speed time-interleaved (TI) SAR ADC with background timing-skew calibration. A time-interleaved structure is employed to improve the effective sampling rate without sacrificing energy efficiency. SAR ADCs are used for each channel to make good use of device scaling. The proposed ADC architecture incorporates a flash ADC operating at the full sampling rate of the TI ADC. The flash ADC output is multiplexed to resolve MSBs of the SAR channels. Because the full-speed flash ADC does not suffer from timing-skew errors, the flash ADC output is also used as the timing reference to estimate the timing-skew of the SAR ADCs.

High Performance And High Speed Pipelined Adcs

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Author : Manar El-Chammas
language : en
Publisher: Springer Nature
Release Date : 2023-05-19

High Performance And High Speed Pipelined Adcs written by Manar El-Chammas and has been published by Springer Nature this book supported file pdf, txt, epub, kindle and other format this book has been release on 2023-05-19 with Technology & Engineering categories.

This book discusses the theoretical foundations and design techniques needed to effectively design high-speed (multi-GS/s) and high-performance pipelined ADCs, which play a critical role in the signal chain of various systems. Readers will be walked through the design and analysis of pipelined ADCs and their topologies, and will learn both theoretical and practical design details that will enable them to explore and build these data converters. The author also presents details on various aspects of pipelined ADCs and their impact on the ADC speed and performance, with a focus on the input buffer and sampling network, the reference amplifier, comparators and their impact on ADC error rate and high-frequency performance, and mismatch estimation and correction.

Low Power High Speed Adcs For Nanometer Cmos Integration

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Author : Zhiheng Cao
language : en
Publisher: Springer Science & Business Media
Release Date : 2008-07-15

Low Power High Speed Adcs For Nanometer Cmos Integration written by Zhiheng Cao and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2008-07-15 with Technology & Engineering categories.

Low-Power High-Speed ADCs for Nanometer CMOS Integration is about the design and implementation of ADC in nanometer CMOS processes that achieve lower power consumption for a given speed and resolution than previous designs, through architectural and circuit innovations that take advantage of unique features of nanometer CMOS processes. A phase lock loop (PLL) clock multiplier has also been designed using new circuit techniques and successfully tested. 1) A 1.2V, 52mW, 210MS/s 10-bit two-step ADC in 130nm CMOS occupying 0.38mm2. Using offset canceling comparators and capacitor networks implemented with small value interconnect capacitors to replace resistor ladder/multiplexer in conventional sub-ranging ADCs, it achieves 74dB SFDR for 10MHz and 71dB SFDR for 100MHz input. 2) A 32mW, 1.25GS/s 6-bit ADC with 2.5GHz internal clock in 130nm CMOS. A new type of architecture that combines flash and SAR enables the lowest power consumption, 6-bit >1GS/s ADC reported to date. This design can be a drop-in replacement for existing flash ADCs since it does require any post-processing or calibration step and has the same latency as flash. 3) A 0.4ps-rms-jitter (integrated from 3kHz to 300MHz offset for >2.5GHz) 1-3GHz tunable, phase-noise programmable clock-multiplier PLL for generating sampling clock to the SAR ADC. A new loop filter structure enables phase error preamplification to lower PLL in-band noise without increasing loop filter capacitor size.