An Fpga Implementation Of The Advanced Encryption Standard With Support For Counter And Feedback Modes
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An Fpga Implementation Of The Advanced Encryption Standard With Support For Counter And Feedback Modes
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Author : James Steven Grabowski
language : en
Publisher:
Release Date : 2007
An Fpga Implementation Of The Advanced Encryption Standard With Support For Counter And Feedback Modes written by James Steven Grabowski and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2007 with categories.
The Advanced Encryption Standard (AES) is a symmetric key block cipher approved by the National Institute of Standards and Technology (NIST). AES replaced the Data Encryption Standard (DES) as a standard encryption algorithm within the United States government. It is widely used in both software and hardware applications and transactions. Different confidentiality modes of operation allow a symmetric key block cipher to provide additional data confidentiality by altering the output in respect to previously processed input data. These modes include Cipher Block Chaining, Cipher Feedback, Output Feedback and Counter modes. Electronic Codebook (ECB) mode does not enhance the confidentiality of the original cipher. This thesis presents an implementation of AES on a field-programmable gate array (FPGA). The design improves upon similar implementations that only employ ECB mode by supporting all five confidentiality modes of operation. The unified design supports all applicable key sizes and offers competitive throughput and resource utilization compared to designs lacking additional confidentiality modes. The design occupies 7452 slices of a Xilinx Virtex-II Pro XC2VP50 and features a maximum clock speed of 56.3 MHz. Throughputs up to 480.427 Mbps, 423.906 Mbps and 379.284 Mbps for 128-bit, 192-bit and 256-bit keys are produced for all five modes of operation. A straightforward level of key agility allows encryption and decryption operations to proceed uninterrupted at the expense of throughput. This feature is ideal when it is necessary to change the key for each block of data. A physical hardware prototype of the design is employed as further demonstration of the design's functional abilities.
Master S Theses Directories
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Author :
language : en
Publisher:
Release Date : 2007
Master S Theses Directories written by and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2007 with Dissertations, Academic categories.
"Education, arts and social sciences, natural and technical sciences in the United States and Canada".
Proceedings Of Technical Papers
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Author :
language : en
Publisher:
Release Date : 2005
Proceedings Of Technical Papers written by and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2005 with Integrated circuits categories.
International Symposium On Computer And Information Sciences
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Author : Erol Gelenbe
language : en
Publisher: CRC Press
Release Date : 2002-10-30
International Symposium On Computer And Information Sciences written by Erol Gelenbe and has been published by CRC Press this book supported file pdf, txt, epub, kindle and other format this book has been release on 2002-10-30 with Computers categories.
Papers from an October 2002 symposium describe research in areas including algorithms, artificial intelligence, computer graphics, computer networks, databases, evolutionary computation, graph theory, image processing, multimedia technology, software engineering, and software performance engineering. Some specific topics are packet selection in a deflection routing algorithm, honeycomb subdivision, a new image-based lighting method, visualizing transition diagrams of action language programs, and solution stability in evolutionary computation. Other subjects include control of lightpaths in heterogeneous optical networks, exploiting semantic constraints in a database browser, and bandwidth allocation in bluetooth scatternets. There is no subject index. Annotation copyrighted by Book News, Inc., Portland, OR
System On Chip Architectures And Implementations For Private Key Data Encryption
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Author : Máire McLoone
language : en
Publisher: Springer Science & Business Media
Release Date : 2012-12-06
System On Chip Architectures And Implementations For Private Key Data Encryption written by Máire McLoone and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2012-12-06 with Computers categories.
In System-on-Chip Architectures and Implementations for Private-Key Data Encryption, new generic silicon architectures for the DES and Rijndael symmetric key encryption algorithms are presented. The generic architectures can be utilised to rapidly and effortlessly generate system-on-chip cores, which support numerous application requirements, most importantly, different modes of operation and encryption and decryption capabilities. In addition, efficient silicon SHA-1, SHA-2 and HMAC hash algorithm architectures are described. A single-chip Internet Protocol Security (IPSec) architecture is also presented that comprises a generic Rijndael design and a highly efficient HMAC-SHA-1 implementation. In the opinion of the authors, highly efficient hardware implementations of cryptographic algorithms are provided in this book. However, these are not hard-fast solutions. The aim of the book is to provide an excellent guide to the design and development process involved in the translation from encryption algorithm to silicon chip implementation.
Fpga Architectures For Cryptography
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Author : Francis Michael Crowe
language : en
Publisher:
Release Date : 2007
Fpga Architectures For Cryptography written by Francis Michael Crowe and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2007 with Field programmable gate arrays categories.
The volume of sensitive electronic transactions taking place over insecure media such as the Internet has increased dramatically in recent years. Cryptography is the main tool by which the transmission and storage of information ranging from an individual{u2019}s credit card details to classified government data is kept secure. This thesis investigates flexible hardware architectures for the main components of a cryptographic system, including confidentiality, authentication, integrity and non-repudiation. Each of the circuits proposed are analysed in terms of their speed, area and efficiency, and the trade-off in terms of performance for flexibility is discussed. Field Programmable Gate Arrays (FPGAs) are chosen as the platform for implementation due to the fast development time and the dedicated arithmetic logic that these devices provide. An investigation of algorithms for encryption and authentication is performed initially. A design of the Advanced Encryption Standard (AES) is described, which supports encryption and decryption, key scheduling and feedback modes of operation. Iterative and unrolled designs of a Secure Hash Algorithm (SHA) are presented, and a comparison is made between them in order to identify the most efficient structure. Architectures for public key cryptography are also proposed in this thesis. A modular exponentiation architecture based on Montgomery modular multiplication is presented, which is suitable for public key schemes such as RSA and digital signatures. Two integrated modular units that support the underlying arithmetic of elliptic curve cryptography (ECC) over large prime characteristic fields are described. A new algorithm for modular inversion is proposed, which results in an improvement in performance over previous inverter designs. The overlap in the underlying arithmetic of the RSA and ECC schemes is also exploited in a dual mode public key processor design, which supports the disparate key sizes of both schemes efficiently. An implementation combining both symmetric and public key algorithms on a PCI prototyping card is proposed. This architecture supports data encryption and authentication in parallel, as well as digital signatures and key exchange. The final part of this thesis deals with the arithmetic of pairing-based cryptography, which has generated extensive research interest in recent years. An architecture for the Tate pairing over large prime characteristic fields is proposed, which requires less FPGA resources than existing Tate pairing designs over low characteristic fields.
Fpga Implementation Of Advanced Encryption Standard Algorithm
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Author : Leelarani Vanapalli
language : en
Publisher: LAP Lambert Academic Publishing
Release Date : 2012-06
Fpga Implementation Of Advanced Encryption Standard Algorithm written by Leelarani Vanapalli and has been published by LAP Lambert Academic Publishing this book supported file pdf, txt, epub, kindle and other format this book has been release on 2012-06 with categories.
'DATA' has an important role in the modern world.With the increasing use of computers in a wide range of applications, the amount of data being processed and operated on had increased tremendously over the years. At the same time protection of data during transmission or while in storage may be necessary to maintain the confidentiality and integrity of the information represented by the data. In applications such as storage and transmission of Federal Information, ATM's and in the Internet there is a lot of emphasis for Data Security. This led to the origin of a new field called 'Cryptography' which deals with the DATA and its security.Public key and secret key cryptographic algorithms provide a solution to this security problem.They ensure data authenticity, integrity and confidentiality. The most widely used secret key algorithm at present is Advanced Encryption Standard(AES) Algorithm.AES was considered over, all the other encryption algorithms because of its increased security levels. The work presented in this book deals with the hardware implementation of the AES algorithm which includes writing a Verilog HDL code for the algorithm and synthesizing it on the FPGA board.
Mathematical Analysis Modes Of Operation And Optimized Fpga Implementation Of 128 Bit Aes Encryption
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Author : Christopher D. Caltagirone
language : en
Publisher:
Release Date : 2002
Mathematical Analysis Modes Of Operation And Optimized Fpga Implementation Of 128 Bit Aes Encryption written by Christopher D. Caltagirone and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2002 with categories.
Design And Implementation Of The Advanced Encryption Standard Aes Using Field Programmable Gate Arrays Fpga
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Author : Syaiful Anuar Zakaria
language : en
Publisher:
Release Date : 2006
Design And Implementation Of The Advanced Encryption Standard Aes Using Field Programmable Gate Arrays Fpga written by Syaiful Anuar Zakaria and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2006 with Data encryption (Computer science) categories.
Reliable And High Performance Hardware Architectures For The Advanced Encryption Standard Galois Counter Mode
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Author : Mehran Mozaffari Kermani
language : en
Publisher:
Release Date : 2011
Reliable And High Performance Hardware Architectures For The Advanced Encryption Standard Galois Counter Mode written by Mehran Mozaffari Kermani and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2011 with categories.
The high level of security and the fast hardware and software implementations of the Advanced Encryption Standard (AES) have made it the first choice for many critical applications. Since its acceptance as the adopted symmetric-key algorithm, the AES has been utilized in various security-constrained applications, many of which are power and resource constrained and require reliable and efficient hardware implementations. In this thesis, first, we investigate the AES algorithm from the concurrent fault detection point of view. We note that in addition to the efficiency requirements of the AES, it must be reliable against transient and permanent internal faults or malicious faults aiming at revealing the secret key. This reliability analysis and proposing efficient and effective fault detection schemes are essential because fault attacks have become a serious concern in cryptographic applications. Therefore, we propose, design, and implement various novel concurrent fault detection schemes for different AES hardware architectures. These include different structure-dependent and independent approaches for detecting single and multiple stuck-at faults using single and multi-bit signatures. The recently standardized authentication mode of the AES, i.e., Galois/Counter Mode (GCM), is also considered in this thesis. We propose efficient architectures for the AESGCM algorithm. In this regard, we investigate the AES algorithm and we propose lowcomplexity and low-power hardware implementations for it, emphasizing on its nonlinear transformation, i.e., SubByes (S-boxes). We present new formulations for this transformation and through exhaustive hardware implementations, we show that the proposed architectures outperform their counterparts in terms of efficiency. Moreover, we present parallel, high-performance new schemes for the hardware implementations of the GCM to improve its throughput and reduce its latency. The performance of the proposed efficient architectures for the AES-GCM and their fault detection approaches are benchmarked using application-specific integrated circuit (ASIC) and field-programmable gate array (FPGA) hardware platforms. Our comparison results show that the proposed hardware architectures outperform their existing counterparts in terms of efficiency and fault detection capability.