Background Digital Calibration Of Sar Adc With Fast Fpga Emulation

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Background Digital Calibration Of Sar Adc With Fast Fpga Emulation

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Author : Guanhua Wang
language : en
Publisher:
Release Date : 2013

Background Digital Calibration Of Sar Adc With Fast Fpga Emulation written by Guanhua Wang and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2013 with Analog-to-digital converters categories.

This dissertation presents a background calibration technique of successive approximation register (SAR) analog-to-digital converter (ADC) and a FPGA emulation platform for fast verification. The bit-weight calibration of a sub-binary weighted SAR ADC is based on the internal redundancy dithering (IRD) technique. A coarse ADC is employed as the reference path to remove the input interference problem in correlation-based background calibration. A custom FPGA emulation platform is developed to verify the proposed calibration approach, which achieves a 3000 speedup for the same simulation executed on a general-purpose microprocessor. Emulation results show that the signal-to-noise plus distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are improved from 56dB to 89dB and 64dB to 115dB, respectively, for a sub-binary-weighted 16-bit SAR ADC with 1% DAC mismatch errors.

Low Power High Performance Sar Adc With Redundancy And Digital Background Calibration

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Author : Albert Hsu Ting Chang
language : en
Publisher:
Release Date : 2013

Low Power High Performance Sar Adc With Redundancy And Digital Background Calibration written by Albert Hsu Ting Chang and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2013 with categories.

As technology scales, the improved speed and energy eciency make the successive- approximation-register (SAR) architecture an attractive alternative for applications that require high-speed and high-accuracy analog-to-digital converters (ADCs). In SAR ADCs, the key linearity and speed limiting factors are capacitor mismatch and incomplete digital-to-analog converter (DAC)/reference voltage settling. In this the- sis, a sub-radix-2 SAR ADC is presented with several new contributions. The main contributions include investigation of using digital error correction (redundancy) in SAR ADCs for dynamic error correction and speed improvement, development of two new calibration algorithms to digitally correct for manufacturing mismatches, design of new architecture to incorporate redundancy within the architecture itself while achieving 94% better energy eciency compared to conventional switching algorithm, development of a new capacitor DAC structure to improve the SNR by four times with improved matching, joint design of the analog and digital circuits to create an asynchronous platform in order to reach the targeted performance, and analysis of key circuit blocks to enable the design to meet noise, power and timing requirements. The design is fabricated in standard 1P9M 65nm CMOS technology with 1.2V supply. The active die area is 0.083mm2 with full rail-to-rail input swing of 2.4V p-p . A 67.4dB SNDR, 78.1dB SFDR, +1.0/-0.9 LSB12 INL and +0.5/-0.7 LSB12 DNL are achieved at 50MS/s at Nyquist rate. The total power consumption, including the estimated calibration and reference power, is 2.1mW, corresponding to 21.9fJ/conv.- step FoM. This ADC achieves the best FoM of any ADCs with greater than 10b ENOB and 10MS/s sampling rate.

Time Interleaved Sar Adc With Signal Independent Background Timing Calibration

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Author : Christopher Kaiti Su
language : en
Publisher:
Release Date : 2020

Time Interleaved Sar Adc With Signal Independent Background Timing Calibration written by Christopher Kaiti Su and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2020 with categories.

This thesis describes a background-calibration technique that overcomes timing errors in time-interleaved analog-to-digital converters (ADCs) in a way that is almost independent of the user-provided ADC input signal. Additive dither is widely used to achieve signal-independent background calibration of many errors in data converters [1]. For example, this technique has been used to calibrate for gain mismatch in time-interleaved ADCs [2]. In most cases, however, binary dither has been used, and binary dither is not able to detect timing errors when the user-provided ADC input is zero or constant because timing errors do not produce amplitude errors when the ADC input is constant. This thesis presents a study of the use of a random ramp-based dither signal to calibrate for timing errors in time-interleaved ADCs. To demonstrate the dither-based timing calibration, a prototype 10-bit 500-MS/s 4-channel ADC was fabricated in 40-nm CMOS. With the proposed timing calibration, the Signal-to-Noise-and-Distortion Ratio (SNDR) is 50.1 dB with a user-provided input at 249 MHz while consuming 6.2 mW, giving a figure of merit (FoM) of 48.4 fJ/step. Disabling the ramp after the timing calibration converges improves the SNDR to 51 dB and reduces the power dissipation to 5.8 mW as well as the FoM to 39.8 fJ/step. [1] H. E. Hilton, "A 10-MHz Analog-to-Digital Converter with 110-dB Linearity," Hewlett-Packard Journal, vol. 44, No. 5, pp. 105-112, Oct. 1993. [2] D. Fu, K. C. Dyer, P. J. Hurst, and S. H. Lewis, "A Digital Background Calibration Technique for Time-Interleaved Analog-to-Digital Converters," IEEE J. of Solid-State Circuits, vol. 33, No. 12, pp.1904-1911, Dec. 1998.

Background Digital Calibration Techniques For High Speed High Resolution Analog To Digital Data Converters

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Author : Yun-Shiang Shu
language : en
Publisher:
Release Date : 2008

Background Digital Calibration Techniques For High Speed High Resolution Analog To Digital Data Converters written by Yun-Shiang Shu and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2008 with categories.

A high-speed, high-resolution analog-to-digital converter (ADC) is a key component in broadband communication transceivers, video imaging systems, and instrumentation. As the ADC speed increases with the advances in IC fabrication technology, the ADC resolution is still limited by the non-ideal effects of the circuits, such as device inaccuracy, component mismatch, and finite device gain. A recent trend for enhancing the resolution is to calibrate the non-ideal effects in background with the aid of digital signal processing. These techniques are preferred since the calibration accuracy is not limited by the accuracy of the analog components, and the calibration tracks the variations of process, voltage and temperature without interrupting ADC's normal operation. This dissertation describes the background calibration techniques for three high-speed, high-resolution ADCs using different architectures: pipelined, floating-point, and continuous-time (CT) [delta]-[sigma]. For pipelined ADCs, a background digital calibration technique with signal-dependent dithering scheme is proposed to overcome the dither magnitude and measurement time constraints with the existing fixed-magnitude dithering. A 15-b, 20-MS/s prototype ADC achieves a spurious-free dynamic range (SFDR) of 98 dB and a peak signal-to-noise plus distortion ratio (SNDR) of 73 dB. The chip is fabricated in 0.18-um complementary metal-oxide-semiconductor (CMOS) process, occupies an active area of 2.3 x 1.7 mm2, and consumes 285 mW at 1.8 V. The concept of signal-dependent dithering is also applied to a floating-point ADC (FADC) to calibrate the gain and offset errors in the variable gain amplifier (VGA) stages. A digitally-calibrated 10~15-b 60-MS/s FADC adjusts its quantization steps instantly depending on the sampled input level and enhances the integral non-linearity (INL) from 24 to 0.9 least significant bit (LSB) at a 15-b level for small input signals. The chip is fabricated in 0.18-um CMOS process, occupies 3.5 x 2.5 mm2, and consumes 300 mW at 1.8 V. In the CT [delta]-[sigma] architecture, the active filter is calibrated by injecting a binary pulse dither and nulling it with an LMS algorithm. The proposed technique calibrates the filter time-constant continuously with crystal accuracy, while the conventional master-slave approaches use additional analog components which limit the calibration accuracy. A 3rd-order 4-b prototype in 65-nm CMOS occupies 0.5 mm2 and consumes 50 mW at 1.3 V. It achieves a dynamic range (DR) of 81 dB over an 8-MHz signal bandwidth with a 2.4 Vpp full-scale range. Signal-to-noise ratio (SNR) and SNDR at -1 dBFS are 76 and 70 dB, respectively.

Nested Digital Background Calibration Of Pipelined Analog To Digital Converters

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Author : Xiaoyue Wang
language : en
Publisher:
Release Date : 2003

Nested Digital Background Calibration Of Pipelined Analog To Digital Converters written by Xiaoyue Wang and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2003 with categories.

Background Analog And Digital Calibration Techniques For Pipelined Adc S

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Author : Sudipta Sarkar
language : en
Publisher:
Release Date : 2017

Background Analog And Digital Calibration Techniques For Pipelined Adc S written by Sudipta Sarkar and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2017 with Comparator circuits categories.

A digital background calibration technique to treat capacitor mismatch, residue gain error and nonlinearity in a pipelined analog-to-digital converter (ADC) based on the split-ADC architecture (J. McNeill et al., “Split ADC architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC,” IEEE J. of Solid-State Circuits, vol. 40, pp. 2437-2445, Dec. 2005) is reported. Although multiple works have been reported before on the split-calibration of pipelined analog-to-digital converters, none of them is comprehensive, i.e., capacitor mismatch, residue gain error and nonlinearity are never treated in one work at the same time. We, for the first time, recognize the multistage pipelined ADC with residue non-linearity calibration as a Nonlinear Least Squares problem. Behavioral simulation results demonstrate the efficacy of the technique, in which the signal-to-noise-and-distortion ratio (SNDR) and spurious-free-dynamic-range (SFDR) performance of a 15-bit split-pipelined ADC are improved from 42 dB and 50 dB to 88 dB and 102 dB on average, respectively. Secondly, an 8b, 1.3/1.39GS/s, 7/8.1mW two-step ADC is presented that introduces a single reference comparator based background comparator offset calibration technique. This work employs a dual-residue based inter-stage redundancy scheme to relax residue amplifier specifications (and enable high-speed operation at 0.85V supply) in a two-step ADC. Comparator offset calibration is implemented through body biasing with an area-efficient 8b offset calibration DAC. A prototype in 28nm Complementary Metal Oxide Semiconductor (CMOS) achieves 6.8 effective number of bits (ENOB) and 50fJ/c-s at DC and 6.3 ENOB and 68fJ/c-s at Nyquist, at a sample rate of 1.3GS/s. The measured SNDR/SFDR improve from 29.2/40.7dB to 42.6/57.7dB after calibration. The active area is 0.05mm2.

A Background Digital Calibration Of Split Capacitor 16 Bit Sar Adc With Sub Binary Architecture

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Author :
language : en
Publisher:
Release Date : 2015

A Background Digital Calibration Of Split Capacitor 16 Bit Sar Adc With Sub Binary Architecture written by and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2015 with categories.

Nested Digital Background Calibration Of A 12 Bit Pipelined Adc Without An Input Sha

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Author : Haoyue Wang
language : en
Publisher:
Release Date : 2008

Nested Digital Background Calibration Of A 12 Bit Pipelined Adc Without An Input Sha written by Haoyue Wang and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2008 with categories.

Applying The Split Adc Architecture To A 16 Bit 1 Ms S Differential Successive Approximation Analog To Digital Converter

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Author :
language : en
Publisher:
Release Date : 2008

Applying The Split Adc Architecture To A 16 Bit 1 Ms S Differential Successive Approximation Analog To Digital Converter written by and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2008 with Analog-to-digital converters categories.

Abstract: Successive Approximation (SAR) analog-to-digital converters are used extensively in biomedical applications such as CAT scan due to the high resolution they offer. Capacitor mismatch in the SAR converter is a limiting factor for its accuracy and resolution. Without some form of calibration, a SAR converter can only achieve 10 bit accuracy. In industry, the CAL-DAC approach is a popular approach for calibrating the SAR ADC, but this approach requires significant test time. This thesis applies the "Split-ADC" architecture with a deterministic, digital, and background self-calibration algorithm to the SAR converter to minimize test time. In this approach, a single ADC is split into two independent halves. The two split ADCs convert the same input sample and produce two output codes. The ADC output is the average of these two output codes. The difference between these two codes is used as a calibration signal to estimate the errors of the calibration parameters in a modified Jacobi method. The estimates are used to update calibration parameters are updated in a negative feedback LMS procedure. The ADC is fully calibrated when the difference signal goes to zero on average. This thesis focuses on the specific implementation of the "Split-ADC" self-calibrating algorithm on a 16 bit, 1 MS/s differential SAR ADC. The ADC can be calibrated with 105 conversions. This represents an improvement of 3 orders of magnitude over existing statistically-based calibration algorithms. Simulation results show that the linearity of the calibrated ADC improves to within "1 LSB.

Digital Background Calibration Of A 10 B 40 Ms S Parallel Pipelined Adc

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Author : Daihong Fu
language : en
Publisher:
Release Date : 1998

Digital Background Calibration Of A 10 B 40 Ms S Parallel Pipelined Adc written by Daihong Fu and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 1998 with categories.