Low Power High Performance Sar Adc With Redundancy And Digital Background Calibration
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Low Power High Performance Sar Adc With Redundancy And Digital Background Calibration
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Author : Albert Hsu Ting Chang
language : en
Publisher:
Release Date : 2013
Low Power High Performance Sar Adc With Redundancy And Digital Background Calibration written by Albert Hsu Ting Chang and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2013 with categories.
As technology scales, the improved speed and energy eciency make the successive- approximation-register (SAR) architecture an attractive alternative for applications that require high-speed and high-accuracy analog-to-digital converters (ADCs). In SAR ADCs, the key linearity and speed limiting factors are capacitor mismatch and incomplete digital-to-analog converter (DAC)/reference voltage settling. In this the- sis, a sub-radix-2 SAR ADC is presented with several new contributions. The main contributions include investigation of using digital error correction (redundancy) in SAR ADCs for dynamic error correction and speed improvement, development of two new calibration algorithms to digitally correct for manufacturing mismatches, design of new architecture to incorporate redundancy within the architecture itself while achieving 94% better energy eciency compared to conventional switching algorithm, development of a new capacitor DAC structure to improve the SNR by four times with improved matching, joint design of the analog and digital circuits to create an asynchronous platform in order to reach the targeted performance, and analysis of key circuit blocks to enable the design to meet noise, power and timing requirements. The design is fabricated in standard 1P9M 65nm CMOS technology with 1.2V supply. The active die area is 0.083mm2 with full rail-to-rail input swing of 2.4V p-p . A 67.4dB SNDR, 78.1dB SFDR, +1.0/-0.9 LSB12 INL and +0.5/-0.7 LSB12 DNL are achieved at 50MS/s at Nyquist rate. The total power consumption, including the estimated calibration and reference power, is 2.1mW, corresponding to 21.9fJ/conv.- step FoM. This ADC achieves the best FoM of any ADCs with greater than 10b ENOB and 10MS/s sampling rate.
High Resolution And High Speed Integrated Cmos Ad Converters For Low Power Applications
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Author : Weitao Li
language : en
Publisher: Springer
Release Date : 2017-08-01
High Resolution And High Speed Integrated Cmos Ad Converters For Low Power Applications written by Weitao Li and has been published by Springer this book supported file pdf, txt, epub, kindle and other format this book has been release on 2017-08-01 with Technology & Engineering categories.
This book is a step-by-step tutorial on how to design a low-power, high-resolution (not less than 12 bit), and high-speed (not less than 200 MSps) integrated CMOS analog-to-digital (AD) converter, to respond to the challenge from the rapid growth of IoT. The discussion includes design techniques on both the system level and the circuit block level. In the architecture level, the power-efficient pipelined AD converter, the hybrid AD converter and the time-interleaved AD converter are described. In the circuit block level, the reference voltage buffer, the opamp, the comparator, and the calibration are presented. Readers designing low-power and high-performance AD converters won’t want to miss this invaluable reference. Provides an in-depth introduction to the newest design techniques for the power-efficient, high-resolution (not less than 12 bit), and high-speed (not less than 200 MSps) AD converter; Presents three types of power-efficient architectures of the high-resolution and high-speed AD converter; Discusses the relevant circuit blocks (i.e., the reference voltage buffer, the opamp, and the comparator) in two aspects, relaxing the requirements and improving the performance.
Low Power High Performance Sar Adc Design With Digital Calibration Techniques
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Author : Wenbo Liu
language : en
Publisher:
Release Date : 2011
Low Power High Performance Sar Adc Design With Digital Calibration Techniques written by Wenbo Liu and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2011 with categories.
Charge Sharing Sar Adcs For Low Voltage Low Power Applications
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Author : Taimur Rabuske
language : en
Publisher: Springer
Release Date : 2016-08-02
Charge Sharing Sar Adcs For Low Voltage Low Power Applications written by Taimur Rabuske and has been published by Springer this book supported file pdf, txt, epub, kindle and other format this book has been release on 2016-08-02 with Technology & Engineering categories.
This book introduces readers to the potential of charge-sharing (CS) successive approximation register (SAR) analog-to-digital converters (ADCs), while providing extensive analysis of the factors that limit the performance of the CS topology. The authors present guidelines and useful techniques for mitigating the limitations of the architecture, while focusing on the implementation under restricted power budgets and voltage supplies.
Techniques For Low Power High Performance Analog To Digital Converters
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Author : Sunghyuk Lee
language : en
Publisher:
Release Date : 2014
Techniques For Low Power High Performance Analog To Digital Converters written by Sunghyuk Lee and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2014 with categories.
Analog-to-digital converters (ADCs) are essential building blocks in many electronic systems which require digital signal processing and storage of analog signals. Traditionally, ADCs are considered a power hungry circuit. This thesis investigates ADC design techniques to achieve high-performance with low power consumption. Two designs are demonstrated. The first design is a voltage scalable zero-crossing based pipelined ADC. The zero-crossing based circuit technique is modified and optimized to improve the limited ADC resolution in nano-scaled CMOS technology. The proposed unidirectional charge transfer scheme allows faster and more energy efficient operation by eliminating unnecessary charging and discharging of the capacitors. Furthermore, the reduced transient disturbance at the beginning of the fine charge transfer phase improves the accuracy of operation. Power supply scaling enhances power efficiency at low sampling rates much like in digital circuits and widens the conversion frequency range where the ADC operates with highest efficiency. The second design is a high speed time-interleaved (TI) SAR ADC with background timing-skew calibration. A time-interleaved structure is employed to improve the effective sampling rate without sacrificing energy efficiency. SAR ADCs are used for each channel to make good use of device scaling. The proposed ADC architecture incorporates a flash ADC operating at the full sampling rate of the TI ADC. The flash ADC output is multiplexed to resolve MSBs of the SAR channels. Because the full-speed flash ADC does not suffer from timing-skew errors, the flash ADC output is also used as the timing reference to estimate the timing-skew of the SAR ADCs.
Time Interleaved Analog To Digital Converters
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Author : Simon Louwsma
language : en
Publisher: Springer Science & Business Media
Release Date : 2010-09-08
Time Interleaved Analog To Digital Converters written by Simon Louwsma and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2010-09-08 with Technology & Engineering categories.
Time-interleaved Analog-to-Digital Converters describes the research performed on low-power time-interleaved ADCs. A detailed theoretical analysis is made of the time-interleaved Track & Hold, since it must be capable of handling signals in the GHz range with little distortion, and minimal power consumption. Timing calibration is not attractive, therefore design techniques are presented which do not require timing calibration. The design of power efficient sub-ADCs is addressed with a theoretical analysis of a successive approximation converter and a pipeline converter. It turns out that the first can consume about 10 times less power than the latter, and this conclusion is supported by literature. Time-interleaved Analog-to-Digital Converters describes the design of a high performance time-interleaved ADC, with much attention for practical design aspects, aiming at both industry and research. Measurements show best-inclass performance with a sample-rate of 1.8 GS/s, 7.9 ENOBs and a power efficiency of 1 pJ/conversion-step.
A 200ms S 12 Bit Subranging Sar Adc
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Author : Brian Elies
language : en
Publisher:
Release Date : 2015
A 200ms S 12 Bit Subranging Sar Adc written by Brian Elies and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2015 with Metal oxide semiconductors, Complementary categories.
The scaling of semiconductor technology results in great improvements in the speed, area and power consumption of transistors. These improvements allow system designers to increase the digital complexity while simultaneously reducing the power consumption, area and cost. This superb digital performance results in an increased demand for analog-to-digital converter (ADC) architectures that can provide high-speed, high-resolution digitization with low power consumption. Unfortunately, many traditional ADC architectures do not receive the same increase in performance as their digital counterparts in deeply scaled CMOS processes. This magnifies the analog design time, effort, complexity and cost of the ADC. Presented here is a subranging architecture that utilizes a coarse pipeline and fine successive approximation register (SAR) ADCs, combined with time interleaving, achieving 12-bit, 200-MS/s. The architecture makes use of analog redundancy to tolerate gain error, nonlinearity and comparator offset caused by the coarse ADC. Dynamic settling errors in the SAR ADC are corrected by sub-radix redundancy. To further improve the performance of the design a calibration mode is proposed to correct capacitor mismatch, channel gain mismatch and channel offset.
Low Power High Speed Adcs For Nanometer Cmos Integration
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Author : Zhiheng Cao
language : en
Publisher: Springer Science & Business Media
Release Date : 2008-07-15
Low Power High Speed Adcs For Nanometer Cmos Integration written by Zhiheng Cao and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2008-07-15 with Technology & Engineering categories.
Low-Power High-Speed ADCs for Nanometer CMOS Integration is about the design and implementation of ADC in nanometer CMOS processes that achieve lower power consumption for a given speed and resolution than previous designs, through architectural and circuit innovations that take advantage of unique features of nanometer CMOS processes. A phase lock loop (PLL) clock multiplier has also been designed using new circuit techniques and successfully tested. 1) A 1.2V, 52mW, 210MS/s 10-bit two-step ADC in 130nm CMOS occupying 0.38mm2. Using offset canceling comparators and capacitor networks implemented with small value interconnect capacitors to replace resistor ladder/multiplexer in conventional sub-ranging ADCs, it achieves 74dB SFDR for 10MHz and 71dB SFDR for 100MHz input. 2) A 32mW, 1.25GS/s 6-bit ADC with 2.5GHz internal clock in 130nm CMOS. A new type of architecture that combines flash and SAR enables the lowest power consumption, 6-bit >1GS/s ADC reported to date. This design can be a drop-in replacement for existing flash ADCs since it does require any post-processing or calibration step and has the same latency as flash. 3) A 0.4ps-rms-jitter (integrated from 3kHz to 300MHz offset for >2.5GHz) 1-3GHz tunable, phase-noise programmable clock-multiplier PLL for generating sampling clock to the SAR ADC. A new loop filter structure enables phase error preamplification to lower PLL in-band noise without increasing loop filter capacitor size.
Design And Implementation Of Radix 3 Radix 2 Based Novel Hybrid Sar Adc In Scaled Cmos Technologies
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Author : Md. Manzur Rahman
language : en
Publisher:
Release Date : 2017
Design And Implementation Of Radix 3 Radix 2 Based Novel Hybrid Sar Adc In Scaled Cmos Technologies written by Md. Manzur Rahman and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2017 with categories.
This thesis focuses on low power and high speed design techniques for successive approximation register (SAR) analog-to-digital converters (ADCs) in nanoscale CMOS technologies. SAR ADCs’ speed is limited by the number of bits of resolution. An N-bit conventional SAR ADC takes N conversion cycles. To speed up the conversion process, we introduce a radix-3 SAR ADC which can compute 1:6 bits per cycle. To our knowledge, it is the first fully programmable and efficiently hardware controlled radix-3 SAR ADC. We had to use two comparators per cycle due to ADC architecture and we proposed a simple calibration scheme for the comparators. Also, as the architecture of the DAC array is completely different from the architecture of conventional radix-2 SAR ADC’s DAC arrays, we came up with an algorithm for calibration of capacitors of the DAC. Low power SAR ADCs face two major challenges especially at high resolutions: (1) increased comparator power to suppress the noise, and (2) increased DAC switching energy due to the large DAC size. Due to our proposed architecture,the radix-3 SAR ADC uses two comparators per cycle and two differential DACs. To improve the comparator’s power efficiency, an efficient and low cost calibration technique has been introduced. It allows a low power and noisy comparator to achieve high signal-to-noise ratio (SNR). To improve the DAC switching energy, we introduced a radix-3/radix-2 based novel hybrid SAR ADC. We use two single ended DACs for radix-3 SAR ADC and these two single ended DACs can be used as one differential DAC for radix-2 SAR ADC. So, overall, we only have a single DAC as conventional radix- 2 SAR ADC. In addition, a monotonic switching technique is adopted for radix-2 search to reduce the DAC capacitor size and hence, to reduce switching power. It can reduce the total number of unit capacitors by four times. Our proposed hybrid SAR ADC can achieve less DAC energy compared to radix-3 and radix-2 SAR ADCs. Also, to utilize technology scaling, we used the minimum capacitor size allowed by thermal noise limitations. To achieve high resolution, we introduced calibration algorithm for the DAC array. As mentioned earlier, the radix-3 SAR ADC offers higher power than conventional radix-2 SAR ADC because of simultaneous use of two comparators. In the proposed hybrid SAR ADC, we will be using radix-3 search for first few MSB bits. So, the resolution required for radix-3 comparators are much larger than the LSB value of 10-bit ADC. By implementing calibration of comparators, we can use low power, high input referred offset and high speed comparators for radix-3 search. Radix-2 search will be used for rest of the bits and the resolution of the radix-2 comparator has to be less than the required LSB value. So, a high power, low input referred offset and high speed comparator is used for radix-2 search. Also, we introduced clock gating for comparators. So, radix-3 comparators will not toggle during radix-2 search and the radix-2 comparators will be inactive during radix-3 search. By using the aforementioned techniques, the overall comparator power is definitely less than a radix-3 SAR ADC and comparable to a conventional radix-2 SAR ADC. A prototype radix-3/radix-2 based hybrid SAR ADC with the proposed technique is designed and fabricated in 40nm CMOS technology. It achieves an SNDR of 56.9 dB and consumes only 0.38 mW power at 30MS/s, leading to a Walden figure of merit of 21.5 fJ/conv-step.
Next Generation Adcs High Performance Power Management And Technology Considerations For Advanced Integrated Circuits
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Author : Andrea Baschirotto
language : en
Publisher: Springer Nature
Release Date : 2019-10-24
Next Generation Adcs High Performance Power Management And Technology Considerations For Advanced Integrated Circuits written by Andrea Baschirotto and has been published by Springer Nature this book supported file pdf, txt, epub, kindle and other format this book has been release on 2019-10-24 with Technology & Engineering categories.
This book is based on the 18 tutorials presented during the 28th workshop on Advances in Analog Circuit Design. Expert designers present readers with information about a variety of topics at the frontier of analog circuit design, including next-generation analog-to-digital converters , high-performance power management systems and technology considerations for advanced IC design. For anyone involved in analog circuit research and development, this book will be a valuable summary of the state-of-the-art in these areas. Provides a summary of the state-of-the-art in analog circuit design, written by experts from industry and academia; Presents material in a tutorial-based format; Includes coverage of next-generation analog-to-digital converters, high-performance power management systems, and technology considerations for advanced IC design.