Design And Evaluation Of An Fpga Based Hardware Accelerator For Elliptic Curve Cryptography Point Multiplication
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Design And Evaluation Of An Fpga Based Hardware Accelerator For Elliptic Curve Cryptography Point Multiplication
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Author : Kapil A. Gwalani
language : en
Publisher:
Release Date : 2009
Design And Evaluation Of An Fpga Based Hardware Accelerator For Elliptic Curve Cryptography Point Multiplication written by Kapil A. Gwalani and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2009 with Cryptography categories.
Smart Computing And Communication
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Author : Meikang Qiu
language : en
Publisher: Springer Nature
Release Date : 2021-04-16
Smart Computing And Communication written by Meikang Qiu and has been published by Springer Nature this book supported file pdf, txt, epub, kindle and other format this book has been release on 2021-04-16 with Computers categories.
This book constitutes the proceedings of the 5th International Conference on Smart Computing and Communication, SmartCom 2020, which took place in Paris, France, during December 29-31, 2020. The 30 papers included in this book were carefully reviewed and selected from 162 submissions. The scope of SmartCom 2020 was broad, from smart data to smart communications, from smart cloud computing to smart security. The conference gathered all high-quality research/industrial papers related to smart computing and communications and aimed at proposing a reference guideline for further research.
Lattice Based Public Key Cryptography In Hardware
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Author : Sujoy Sinha Roy
language : en
Publisher: Springer Nature
Release Date : 2019-11-12
Lattice Based Public Key Cryptography In Hardware written by Sujoy Sinha Roy and has been published by Springer Nature this book supported file pdf, txt, epub, kindle and other format this book has been release on 2019-11-12 with Technology & Engineering categories.
This book describes the efficient implementation of public-key cryptography (PKC) to address the security challenges of massive amounts of information generated by the vast network of connected devices, ranging from tiny Radio Frequency Identification (RFID) tags to powerful desktop computers. It investigates implementation aspects of post quantum PKC and homomorphic encryption schemes whose security is based on the hardness of the ring-learning with error (LWE) problem. The work includes designing an FPGA-based accelerator to speed up computation on encrypted data in the cloud computer. It also proposes a more practical scheme that uses a special module called recryption box to assist homomorphic function evaluation, roughly 20 times faster than the implementation without this module.
A Modular Design Of Elliptic Curve Point Multiplication For Resource Constrained Devices
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Author :
language : en
Publisher:
Release Date :
A Modular Design Of Elliptic Curve Point Multiplication For Resource Constrained Devices written by and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on with categories.
Elliptic curve cryptography (ECC) is a good candidate for protecting secret data on resource constrained devices. FPGA-based implementations of its main operation, i.e., scalar point multiplication, have gained popularity for their apparent speed advantage over the software counterparts. This paper presents a simple design of point multiplication that minimizes the occupied FPGA resources while maintaining an acceptable timing performance. This is achieved by employing Montgomery ladder algorithm in the projective field, simplest arithmetic units and optimized schedule for the operations. Due to the modular design approach adopted, our design can be easily adapted to different implementation requirements.
Hardware Software Optimizations For Elliptic Curve Scalar Multiplication On Hybrid Fpgas
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Author : Glenn Ramsey
language : en
Publisher:
Release Date : 2008
Hardware Software Optimizations For Elliptic Curve Scalar Multiplication On Hybrid Fpgas written by Glenn Ramsey and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2008 with Computer security categories.
"Elliptic curve cryptography (ECC) offers a viable alternative to Rivest-Shamir-Adleman (RSA) by delivering equivalent security with a smaller key size. This has several advantages, including smaller bandwidth demands, faster key exchange, and lower latency encryption and decryption. The fundamental operation for ECC is scalar point multiplication, wherein a point P on an elliptic curve defined over a finite field is multiplied by a scalar k. The complexity of this operation requires a hardware implementation to achieve high performance. The algorithms involved in scalar point multiplication are constantly evolving, incorporating the latest developments in number theory to improve computation time. These competing needs, high performance and flexibility, have caused previous implementations to either limit their adaptability or to incur performance losses. This thesis explores the use of a hybrid-FPGA for scalar point multiplication. A hybrid-FPGA contains a general purpose processor (GPP) in addition to reconfigurable fabric. This allows for a software/hardware co-design with low latency communication between the GPP and custom hardware. The elliptic curve operations and finite field inversion are programmed in C code. All other finite field arithmetic is implemented in the FPGA hardware, providing higher performance while retaining flexibility. The resulting implementation achieves speedups ranging from 24 times to fastermes fster than an optimized software implementation executing on a Pentium II workstation. The scalability of the design is investigated in two directions: faster finite field multiplication and increased instruction level parallelism exploitation. Increasing the number of parallel arithmetic units beyond two is shown to be less efficient than increasing the speed of the finite field multiplier."--Abstract.
Architecture Exploration Of Fpga Based Accelerators For Bioinformatics Applications
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Author : B. Sharat Chandra Varma
language : en
Publisher: Springer
Release Date : 2016-03-02
Architecture Exploration Of Fpga Based Accelerators For Bioinformatics Applications written by B. Sharat Chandra Varma and has been published by Springer this book supported file pdf, txt, epub, kindle and other format this book has been release on 2016-03-02 with Technology & Engineering categories.
This book presents an evaluation methodology to design future FPGA fabrics incorporating hard embedded blocks (HEBs) to accelerate applications. This methodology will be useful for selection of blocks to be embedded into the fabric and for evaluating the performance gain that can be achieved by such an embedding. The authors illustrate the use of their methodology by studying the impact of HEBs on two important bioinformatics applications: protein docking and genome assembly. The book also explains how the respective HEBs are designed and how hardware implementation of the application is done using these HEBs. It shows that significant speedups can be achieved over pure software implementations by using such FPGA-based accelerators. The methodology presented in this book may also be used for designing HEBs for accelerating software implementations in other domains besides bioinformatics. This book will prove useful to students, researchers, and practicing engineers alike.
Efficient Implementation Of Elliptic Curve Cryptography In Reconfigurable Hardware
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Author : E-Jen Lien
language : en
Publisher:
Release Date : 2012
Efficient Implementation Of Elliptic Curve Cryptography In Reconfigurable Hardware written by E-Jen Lien and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2012 with categories.
Elliptic curve cryptography (ECC) has emerged as a promising public-key cryptography approach for data protection. It is based on the algebraic structure of elliptic curves over finite fields. Although ECC provides high level of information security, it involves computationally intensive encryption/decryption process, which negatively affects its performance and energy-efficiency. Software implementation of ECC is often not amenable for resource-constrained embedded applications. Alternatively, hardware implementation of ECC has been investigated - in both application specific integrated circuit(ASIC) and field programmable gate array (FPGA) platforms - in order to achieve desired performance and energy efficiency. Hardware reconfigurable computing platforms such as FPGAs are particularly attractive platform for hardware acceleration of ECC for diverse applications, since they involve significantly less design cost and time than ASIC. In this work, we investigate efficient implementation of ECC in reconfigurable hardware platforms. In particular, we focus on implementing different ECC encryption algorithms in FPGA and a promising memory array based reconfigurable computing framework, referred to as MBC. MBC leverages the benefit of nanoscale memory, namely, high bandwidth, large density and small wire delay to drastically reduce the overhead of programmable interconnects. We evaluate the performance and energy efficiency of these platforms and compare those with a purely software implementation. We use the pseudo-random curve in the prime field and Koblitz curve in the binary field to do the ECC scalar multiplication operation. We perform functional validation with data that is recommended by NIST. Simulation results show that in general, MBC provides better energy efficiency than FPGA while FPGA provides better latency.
Hardware Acceleration Of Eda Algorithms
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Author : Sunil P Khatri
language : en
Publisher: Springer Science & Business Media
Release Date : 2010-03-11
Hardware Acceleration Of Eda Algorithms written by Sunil P Khatri and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2010-03-11 with Technology & Engineering categories.
Single-threaded software applications have ceased to see signi?cant gains in p- formance on a general-purpose CPU, even with further scaling in very large scale integration (VLSI) technology. This is a signi?cant problem for electronic design automation (EDA) applications, since the design complexity of VLSI integrated circuits (ICs) is continuously growing. In this research monograph, we evaluate custom ICs, ?eld-programmable gate arrays (FPGAs), and graphics processors as platforms for accelerating EDA algorithms, instead of the general-purpose sing- threaded CPU. We study applications which are used in key time-consuming steps of the VLSI design ?ow. Further, these applications also have different degrees of inherent parallelism in them. We study both control-dominated EDA applications and control plus data parallel EDA applications. We accelerate these applications on these different hardware platforms. We also present an automated approach for accelerating certain uniprocessor applications on a graphics processor. This monograph compares custom ICs, FPGAs, and graphics processing units (GPUs) as potential platforms to accelerate EDA algorithms. It also provides details of the programming model used for interfacing with the GPUs.
High Speed And Low Complexity Hardware Architectures For Elliptic Curve Based Crypto Processors
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Author : Reza Azarderakhsh
language : en
Publisher:
Release Date : 2011
High Speed And Low Complexity Hardware Architectures For Elliptic Curve Based Crypto Processors written by Reza Azarderakhsh and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2011 with categories.
The elliptic curve cryptography (ECC) has been identified as an efficient scheme for public-key cryptography. This thesis studies efficient implementation of ECC crypto-processors on hardware platforms in a bottom-up approach. We first study efficient and low-complexity architectures for finite field multiplications over Gaussian normal basis (GNB). We propose three new low-complexity digit-level architectures for finite field multiplication. Architectures are modified in order to make them more suitable for hardware implementations specially focusing on reducing the area usage. Then, for the first time, we propose a hybrid digit-level multiplier architecture which performs two multiplications together (double-multiplication) with the same number of clock cycles required as the one for one multiplication. We propose a new hardware architecture for point multiplication on newly introduced binary Edwards and generalized Hessian curves. We investigate higher level parallelization and lower level scheduling for point multiplication on these curves. Also, we propose a highly parallel architecture for point multiplication on Koblitz curves by modifying the addition formulation. Several FPGA implementations exploiting these modifications are presented in this thesis. We employed the proposed hybrid multiplier architecture to reduce the latency of point multiplication in ECC crypto-processors as well as the double-exponentiation. This scheme is the first known method to increase the speed of point multiplication whenever parallelization fails due to the data dependencies amongst lower level arithmetic computations. Our comparison results show that our proposed multiplier architectures outperform the counterparts available in the literature. Furthermore, fast computation of point multiplication on different binary elliptic curves is achieved.
Fpga Based Hardware Accelerators
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Author : Iouliia Skliarova
language : en
Publisher: Springer
Release Date : 2019-05-30
Fpga Based Hardware Accelerators written by Iouliia Skliarova and has been published by Springer this book supported file pdf, txt, epub, kindle and other format this book has been release on 2019-05-30 with Technology & Engineering categories.
This book suggests and describes a number of fast parallel circuits for data/vector processing using FPGA-based hardware accelerators. Three primary areas are covered: searching, sorting, and counting in combinational and iterative networks. These include the application of traditional structures that rely on comparators/swappers as well as alternative networks with a variety of core elements such as adders, logical gates, and look-up tables. The iterative technique discussed in the book enables the sequential reuse of relatively large combinational blocks that execute many parallel operations with small propagation delays. For each type of network discussed, the main focus is on the step-by-step development of the architectures proposed from initial concepts to synthesizable hardware description language specifications. Each type of network is taken through several stages, including modeling the desired functionality in software, the retrieval and automatic conversion of key functions, leading to specifications for optimized hardware modules. The resulting specifications are then synthesized, implemented, and tested in FPGAs using commercial design environments and prototyping boards. The methods proposed can be used in a range of data processing applications, including traditional sorting, the extraction of maximum and minimum subsets from large data sets, communication-time data processing, finding frequently occurring items in a set, and Hamming weight/distance counters/comparators. The book is intended to be a valuable support material for university and industrial engineering courses that involve FPGA-based circuit and system design.