Design And Implementation Of Telemedicine Client Server Model Using Encryption And Decryption Algorithm In Single Core And Multicore Architecture On L
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Design And Implementation Of Telemedicine Client Server Model Using Encryption And Decryption Algorithm In Single Core And Multicore Architecture On L
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Author : Manjunath Basavaiah
language : en
Publisher: GRIN Verlag
Release Date : 2012-03-08
Design And Implementation Of Telemedicine Client Server Model Using Encryption And Decryption Algorithm In Single Core And Multicore Architecture On L written by Manjunath Basavaiah and has been published by GRIN Verlag this book supported file pdf, txt, epub, kindle and other format this book has been release on 2012-03-08 with Computers categories.
Project Report from the year 2011 in the subject Computer Science - Applied, Coventry University (M.S. Ramaiah School of Advanced Studies), course: M. Sc. [Engg] in Real Time Embedded Systems, language: English, abstract: Multimedia applications have an increasing importance in many areas. There is a growing need to store and transmit high quality video for applications where common coding schemes do not yield enough quality. An example of this is Telemedicine system is best example of Applied Medical Informatics. Several physiologic data, Digital images and video can be transmitted more rapidly and easily than conventional images and videos. In telemedicine expert physicians in tertiary care centres can view a digital image, videos and advice local physicians on the best plan of care without having to move the patient many miles away. Telemedicine will be implemented using the TCP client-server model. The clientserver model was originally developed to allow more users to share access to database applications. The data must be secure, when the data is transmitted from server to client, security must ensure that data will not be damaged by attackers and protects against danger, loss, and criminals. Even if someone tries to hack the data content of file should not be revealed to the attacker. So it is necessary to encrypt the data before transmitting the file using encryption methods. The encryption method used in server and client model is XOR or AES (advanced encryption standard) or Rijndael algorithm which is used to encrypt and decrypt the x-ray images of patients, drug prescriptions. The Rijndael algorithm allows encrypt video at high quality while achieving great encryption. This property makes the Rijndael algorithm a good option for building a video encryption able to obtain better performance than other more general purpose algorithms such as XOR or AES algorithm. One of the main problems when working with the video sequence is the huge datasets that have to
Design And Implementation Of Low Power Nano Scale Hardware Based Crypto Systems
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Author : Valliyappan Valliyappan
language : en
Publisher:
Release Date : 2014
Design And Implementation Of Low Power Nano Scale Hardware Based Crypto Systems written by Valliyappan Valliyappan and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2014 with categories.
As the technology advances day by day, there is an essential need for a secured data transmission for exchanging information from one user to the other. Generally , data transmission techniques are achieved via private/public data networks. The transmission of data through these networks is not secured. Therefore, some kind of safety is needed for information exchange which is accomplished by encrypting the transmitted data. In this research a novel method is used in which hardware implementations of private/secret key encryption standards such as Advanced Encryption Standard (AES), Triple Data Encryption Standard (TDES) and Data Encryption Standard (DES) are integrated in a single silicon die of group centric Secured Information Sharing. This improves confidentiality, integrity and accuracy of the transmitted data. Advanced Encryption Standard is specified by National Institute of Standards (NIST) in 2001 as the specifications for encryption in electronic communication. It is also known as symmetric key algorithm as the encryption and decryption both are formulated using this single standard key. From the family of ciphers NIST selected three members of Rijndael family, each with key length of 128, 192 and 256 bits for each 128 bit block size as AES. For every key length a fixed number of rounds in AES are processed. For 128, 192 and 256 bits, 10, 12 and 14 rounds are executed respectively. In this research, AES 128 bits has been designed and implemented. Triple Data Encryption Standard (TDES) is a cipher algorithm where original Data Encryption Algorithm (DEA) or DES is applied three times. When DES was originally developed, it was sufficient to withstand the attacks using computer power of that era. However, with the remarkable increase in computing power, this algorithm was not complex enough to withstand the brutal attacks. To overcome this problem, Triple DES was proposed to offer high level of security without proposing any novel cipher algorithm. In this research all these three algorithms are implemented in Verilog and TSMC 65nm technology node. Xilinx ISE and Icarus Verilog are used for simulation of AES and DES. Cadence RTL Compiler is used to synthesize the design with minimum area. Finally the Graphic Database System (GDS) II layout of all the crypto cores and Top Module have been generated using Cadence Encounter.
An Investigation And Implementation Of Encryption Algorithms For A Client Server Architecture Suitable For A Mobile Phone Application
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Author : Guillermo Navarro
language : en
Publisher:
Release Date : 2001
An Investigation And Implementation Of Encryption Algorithms For A Client Server Architecture Suitable For A Mobile Phone Application written by Guillermo Navarro and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2001 with categories.
A Hardware Implementation Of Hs1 Siv Encryption Algorithm Using System Verilog
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Author : Maththaiya Durai
language : en
Publisher:
Release Date : 2015
A Hardware Implementation Of Hs1 Siv Encryption Algorithm Using System Verilog written by Maththaiya Durai and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2015 with categories.
Information is an organization's most important asset. According to the Identity Theft Resource Center1, there were 761 reported data security breaches in 2014 impacting over 83 million breached records across industries. In today's informational world, Data security is a major concern for everyone. In a layered security model, it is often necessary to implement one final prevention control wrapped around sensitive information: encryption. Encryption is the process of encoding messages or information in such a way that only authorized parties can read it. To ensure security and confidentiality the message is encrypted using an encryption algorithm. The resulting cipher text yields the original message only upon decryption. Hence, encryption is one of the major information security solutions. Hash Stream1-Synthetic Initialization Vector (HS1-SIV) is a recently developed one such encryption algorithm. Identity Theft Resource Center report URL: http://www.idtheftcenter.org/images/breach/ITRC_Breach_Report_2014.pdf In this project, a hardware implementation of the HS1-SIV encryption algorithm is proposed. A unique feature of the proposed pipelined design is that the key generation steps including CHACHA stream cipher, HS1-Hash and HS1-pseudo random function are performed in parallel. This lowers the delay associated with each round of encryption and reduces the overall encryption delay of a plaintext block. This leads to an increase in the message encryption throughput. The project involved designing a hardware realization of HS1-SIV encryption algorithm, modeling the algorithm in System Verilog hardware description language, validating and synthesizing it using a 90nm hardware cell library. The proposed design was thoroughly verified using a System Verilog layered test bench architecture. The extent of verification was measured by using System Verilog Functional Coverage. Verification was performed on Synopsys VCS® tool. The expected results used in validating the implementation were generated, as part of the layered test bench infra-structure. The final phase of the project involved synthesizing the System Verilog model of HS1-SIV encryption algorithm towards a 90 nm technology library. Based on the synthesis results, the pipelined design is a more efficient implementation. It is 121 times faster than the non-pipelined design.
Design And Implementation Of A Customized Encryption Algorithm For Authentication And Secure Communication Between Devices
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Author : Bhavana Daddala
language : en
Publisher:
Release Date : 2017
Design And Implementation Of A Customized Encryption Algorithm For Authentication And Secure Communication Between Devices written by Bhavana Daddala and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2017 with Computer algorithms categories.
Security is one of the biggest concerns in the developing world. It is important to ensure a safe transfer of information between communicating parties, protecting them from attacks. Many standards and developed encryption protocols are available as resources and are used based on the requirements. In this thesis, we propose a customized encryption algorithm and an authentication scheme to safely transfer information. The algorithm is a variation of Advanced Encryption Standard (AES) and is carried out between multiple devices. AES uses only one private key (symmetric key) to encrypt the data. The implementation works on a single standard irreducible polynomial of degree '8' which is further used to compute multiplicative inverse tables, S-boxes and inverse S-Boxes required for the working of every layer in the algorithm. As compared to AES, we use sixteen irreducible polynomials of degree '8' instead of one in our implementation. Key sizes for AES are usually 128, 192 and 256 bits in size; we use a 128-bit key. Unlike symmetric encryption, asymmetric encryption uses two keys, private and public keys. The public keys are shared among the communicating parties, while the private keys are kept secret. The keys are supposed to be large in size to maintain strength. Thus, they usually range from 512 bits to 2048 bits or more for asymmetric cryptography. The communicating parties can start with public-private keys and agree upon a common key (session key) which can be used as a key to AES. Diffie-Hellman key exchange protocol uses a combination of AES and RSA algorithms resulting in reliable cryptosystems. Our algorithm focuses on devising a new protocol for key establishment and agreement, using the combination framework. The implementation of the communication protocol between two devices, with a prospect of working with multiple devices using a centralized server, is presented. The outcome is to establish a different approach towards encryption and enhance security by providing protection against Man-in-the-Middle attacks. The customized algorithms are implemented using Python.
Can Crypto Chip To Secure Data Transmitted Through Can Fd Bus By Using Aes 128 Sha 1 With A Symmetric Key
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Author :
language : en
Publisher:
Release Date : 2017
Can Crypto Chip To Secure Data Transmitted Through Can Fd Bus By Using Aes 128 Sha 1 With A Symmetric Key written by and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2017 with Automobiles categories.
Robert Robert Bosch GmBH proposed in 2012 a new version of communication protocol named as Controller Area Network with Flexible Data-Rate (CANFD), that supports data frames up to 64 bytes compared to 8 bytes of CAN. With limited data frame size of CAN message, and it is impossible to encrypt and secure. With this new feature of CAN FD, I propose a hardware design - CAN crypto FPGA chip to secure data transmitted through CAN FD bus by using AES-128 and SHA-1 algorithms with a symmetric key. Hardware will protect confidentiality of cryptographic keys better than software. AES-128 algorithm provides confidentiality of CAN message and SHA-1 algorithm with a symmetric key (HMAC) provides integrity and authenticity of CAN message. The design has been modeled and verified by using Verilog HDL - a hardware description language, and implemented successfully into Xilinx and Altera FPGA chips by using simulation tool ISE (Xilinx) and Quartus (Altera). Verification are done by applying direct test bench with National Institute of Standards and Technology (NIST) test vectors for AES-128, SHA-1, CAN crypto encryption and decryption cores. The performance of the design implemented into Xilinx FPGA chip (Virtex5 XC5VLX50T) were 187 MHz maximum clock frequency & 203 Mbps throughput for the encryption core, and 182 MHz maximum clock frequency & 198 Mbps throughput for the decryption core. The performance of the design implemented into Altera FPGA Chip (EP4CE115F29C7) were 90.09 MHz maximum clock frequency & 98 Mbps throughput for the encryption core, and 89.13 MHz maximum clock frequency & 97 Mbps throughput for the decryption core. In addition, an ASIC chip of the design has been built successfully by using Synopsys tools, and its performance was 100 MHz maximum clock frequencyfor both the encryption and decryption core. In conclusion, the performance of CAN crypto encryption and decryption cores in both FPGA chips and ASIC chip show that CAN Crypto design is suitable to be embedded into ECUs for securing data transmitted through CAN FD bus. I have enhanced CAN Crypto design by adding 64 bits anti-replay counter to prevent Replay attacks, and using dynamic Cipher Key and Symmetric Key to strengthen robustness of secret of those keys. Moreover, the proposed design is also applicable to secure CAN bus; this makes it more promising to secure hybrid network-an integration of CANFD and CAN buses. The design of enhanced CAN Crypto has been modeled and verified successfully by using Verilog HDL, and implemented successfully into Altera FPGA chip by using Altera Quartus simulation tool, The performance of the enhanced design implemented into Altera FPGA Chip (EP4CE115F29C7) were 87.83 MHz maximum clock frequency & 95 Mbps throughput for the encryption core, and 86.84 MHz maximum clock frequency & 94 Mbps throughput for the decryption core. The performance of enhanced CAN Cryptio encryption and decryption cores shows that enhanced CAN Cryptio design is suitable to be embedded into ECUs for securing data transmitted through CAN FD bus in-vehicle networks. In conclusion, by implementing the CAN Crypto design inside each ECU, we are not only providing authenticity of CAN message but also integrity and confidentiality of the message. This solution will secure CAN networks better than current academic and industrial solutions, which are only providing authenticity of CAN message.
Design And Development Of A Reconfigurable Cryptographic Co Processor
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Author : Daniele Fronte
language : en
Publisher:
Release Date : 2018
Design And Development Of A Reconfigurable Cryptographic Co Processor written by Daniele Fronte and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2018 with categories.
Nowadays hi-tech secure products need more services and more security. Furthermore the corresponding market is now oriented towards more exibility. In this thesis we propose as novel solution a Multi-algorithm Cryptographic Co-processor called Celator. Celator is able to encrypt or decrypt data blocks using private key encryption algorithms such as Advanced Encryption Standard (AES) or Data Encryption Standard (DES) . Moreover Celator allows condensing data using the Secure Hash Algorithms (SHA). These algorithms are frequently implemented in hi-tech secure products in software or in hardware mode. Celator belongs to the class of the exible hardware implementations, and allows an user implementing its own cryptographic algorithm under specific conditions. Celator architecture is based on a 4x4 Processing Elements (PE) systolic array, a Controller with a Finite State Machine (FSM) and a local memory. Data are encrypted or decrypted by the PE array. This thesis presents Celator architecture, as well as its AES, DES, and SHA basic operations. Celator performances are then given and compared to other security circuits.
Design And Implementation Of Encryption Algorithms In A Coarse Grain Reconfigurable Environment
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Author : Jason P. Rhinelander
language : en
Publisher:
Release Date : 2003
Design And Implementation Of Encryption Algorithms In A Coarse Grain Reconfigurable Environment written by Jason P. Rhinelander and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2003 with Adaptive computing systems categories.
Implementation Of Selected Cryptographic Algorithms On A Reconfigurable Microprocessor Platform
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Author : Andrew L. Cook
language : en
Publisher:
Release Date : 2003
Implementation Of Selected Cryptographic Algorithms On A Reconfigurable Microprocessor Platform written by Andrew L. Cook and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2003 with Adaptive computing systems categories.
Cryptographic Security Architecture
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Author : Peter Gutmann
language : en
Publisher: Springer Science & Business Media
Release Date : 2003-10-01
Cryptographic Security Architecture written by Peter Gutmann and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2003-10-01 with Computers categories.
Presents a novel design that allows for a great deal of customization, which many current methods fail to include; Details a flexible, comprehensive design that can be easily extended when necessary; Proven results: the versatility of the design has been effectively tested in implementations ranging from microcontrollers to supercomputers