Design Of High Speed Energy Efficient Successive Approximation Analog To Digital Converters
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Design Of High Speed Energy Efficient Successive Approximation Analog To Digital Converters
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Author : 劉純成
language : en
Publisher:
Release Date : 2010
Design Of High Speed Energy Efficient Successive Approximation Analog To Digital Converters written by 劉純成 and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2010 with categories.
Design Of High Speed Energy Efficient Successive Approximation Register Analog To Digital Converters
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Author : 張廷愷
language : en
Publisher:
Release Date : 2014
Design Of High Speed Energy Efficient Successive Approximation Register Analog To Digital Converters written by 張廷愷 and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2014 with categories.
High Speed Energy Efficient Successive Approximation Analog To Digital Converter Using Tri Level Switching
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Author : Sahar Sarafi
language : en
Publisher:
Release Date : 2015
High Speed Energy Efficient Successive Approximation Analog To Digital Converter Using Tri Level Switching written by Sahar Sarafi and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2015 with categories.
Design Of Energy Efficient Successive Approximation Analog To Digital Converter
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Author : 黃冠穎
language : en
Publisher:
Release Date : 2007
Design Of Energy Efficient Successive Approximation Analog To Digital Converter written by 黃冠穎 and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2007 with categories.
Easily Integrated And Energy Efficient Design Techniques For Successive Approximation Analog To Digital Converters
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Author : 黃冠穎
language : en
Publisher:
Release Date : 2013
Easily Integrated And Energy Efficient Design Techniques For Successive Approximation Analog To Digital Converters written by 黃冠穎 and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2013 with categories.
Digitally Assisted Techniques For Nyquist Rate Analog To Digital Converters
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Author : Rabeeh Majidi
language : en
Publisher:
Release Date : 2015
Digitally Assisted Techniques For Nyquist Rate Analog To Digital Converters written by Rabeeh Majidi and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2015 with categories.
Abstract: With the advance of technology and rapid growth of digital systems, low power high speed analog-to- digital converters with great accuracy are in demand. To achieve high effective number of bits Analog-to-Digital Converter (ADC) calibration as a time consuming process is a potential bottleneck for designs. This dissertation presentsa fully digital background calibration algorithm for a 7- bit redundant flash ADC using split structure and look-up table based correction. Redundant comparators are used in the flash ADC design of this work in order to tolerate large offset voltages while minimizing signal input capacitance. The split ADC structure helps by eliminating the unknown input signal from the calibration path. The flash ADC has been designed in 180nm IBM CMOS technology and fabricated through MOSIS. This work was supported by Analog Devices, Wilmington, MA. While much research on ADC design has concentrated on increasing resolution and sample rate, there are many applications (e.g. biomedical devices and sensor networks) that do not require high performance but do require low power energy efficient ADCs. This dissertation also explores on design of a low quiescent current 100k Sps Successive Approximation (SAR) ADC that has been used as an error detection ADC for an automotive application in 350nm CD (CMOS-DMOS) technology. This work was supported by ON Semiconductor Corp, East Greenwich, RI.
Energy Efficient Analog To Digital Conversion For Ultra Wideband Radio
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Author : Brian Paul Ginsburg
language : en
Publisher:
Release Date : 2007
Energy Efficient Analog To Digital Conversion For Ultra Wideband Radio written by Brian Paul Ginsburg and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2007 with categories.
In energy constrained signal processing and communication systems, a focus on the analog or digital circuits in isolation cannot achieve the minimum power consumption. Furthermore, in advanced technologies with significant variation, yield is traditionally achieved only through conservative design and a sacrifice of energy efficiency. In this thesis, these limitations are addressed with both a comprehensive mixed-signal design methodology and new circuits and architectures, as presented in the context of an analog-to-digital converter (ADC) for ultra-wideband (UWB) radio. UWB is an emerging technology capable of high-data-rate wireless communication and precise locationing, and it requires high-speed (>500MS/s), low-resolution ADCs. The successive approximation register (SAR) topology exhibits significantly reduced complexity compared to the traditional flash architecture. Three time-interleaved SAR ADCs have been implemented. At the mixed-signal optimum energy point, parallelism and reduced voltage supplies provide more than 3x energy savings. Custom control logic, a new capacitive DAC, and a hierarchical sampling network enable the high-speed operation. Finally, only a small amount of redundancy, with negligible power penalty, dramatically improves the yield of the highly parallel ADC in deep sub-micron CMOS.
Energy Efficient Successive Approximation Analog To Digital Converter
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Author : 戴宏彥
language : en
Publisher:
Release Date : 2014
Energy Efficient Successive Approximation Analog To Digital Converter written by 戴宏彥 and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2014 with categories.
Design Techniques For Ultra High Speed Time Interleaved Analog To Digital Converters
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Author : Yida Duan
language : en
Publisher:
Release Date : 2015
Design Techniques For Ultra High Speed Time Interleaved Analog To Digital Converters written by Yida Duan and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2015 with categories.
Analog-to-Digital Converters (ADCs) serve as the interfaces between the analog natural world and the binary world of computer data. Due to this essential role, ADC circuits have been well studied over 40 years, and many problems associated with them have already been solved. However in recent years, a new species of ADCs has appeared, and since then attracted lots of attention. These are ultra-high-speed (often greater than 40GS/s) time-interleaved ADCs of low or medium resolution (around 6 to 8 bit) built in CMOS processes. Although such ADCs can be used in high-speed electronic measurement equipment and radar systems, the recent driving force behind them is next generation 100Gbps/400Gbps fiber optical transceivers. These transceivers take advantage of ultra-high-speed ADCs and digital-signal-processors (DSPs) to enable ultra-high data-rate communications in long-haul networks (city-to-city, transcontinental, and transoceanic fiber links), metro networks (fibers that connect enterprises in metropolitan areas), and data centers (fiber links within data center infrastructures). At such high sampling rate, massively time-interleaved successive-approximation ADC (SAR ADC) architecture has emerged as the dominant solution due to its excellent power efficiency. Several recent works has demonstrated success in achieving high sampling rate. However, the sampling network has become the bottleneck that limits the input bandwidth in these ADCs. It is apparent that conventional switch-based track-and-hold (T&H) circuit cannot satisfy the >20GHz bandwidth requirement. In addition, it is unclear what the optimal interleaving configuration is. Each state-of-the-art design adopts a different interleaving configuration - from straightforward conventional 1-rank interleaving to 2-rank hierarchical sampling or even 3 ranks. How to partition interleaving factors among different ranks has not yet been investigated. Furthermore, asynchronous SAR sub-ADCs are often used in these designs to push the sampling rate even further. The well-known sparkle-code issues caused by comparator meta-stability in asynchronous SARs can significantly increase the Bit-Error-Rate (BER) of the transceivers unless power hungry error correction coding are implemented in the system. Although many works in the literature attempted to deal with the meta-stability in asynchronous SARs, the effectiveness of these approaches have not been fully demonstrated. In this thesis, I will first propose a new cascode-based T&H circuits to improve the ADC bandwidth beyond the limit of conventional switch-based T&H circuits. Then, a system design and optimization methodology of hierarchical time-interleaved sampling network is presented in the context of cascode T&H. To deal with sparkle-code issue in asynchronous SAR sub-ADCs, a new back-end meta-stability correction technique is employed. An extensive statistical analysis is provided to verify the correction algorithm can greatly reduce sparkle-code error-rates. To further demonstrate the effectiveness of the proposed circuits and techniques, two prototype ADCs have been implemented. The first 7b 12.5GS/s hierarchically time-interleaved ADC in 65nm CMOS process demonstrates 29.4dB SNDR and >25GHz bandwidth. The later 6b 46GS/s ADC in 28nm CMOS employs asynchronous SAR sub-ADC design with back-end meta-stability correction. The measurement results show it achieves sparkle-code error free operation over 1e10 samples in addition to achieving >23GHz bandwidth and 25.2dB SNDR. The power consumption is 381mW from 1.05V/1.6V supplies, and the FOM is 0.56pJ/conversion-step.
Design Of Energy Efficient A D Converters With Partial Embedded Equalization For High Speed Wireline Receiver Applications
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Author : Ehsan Zhian Tabasy
language : en
Publisher:
Release Date : 2015
Design Of Energy Efficient A D Converters With Partial Embedded Equalization For High Speed Wireline Receiver Applications written by Ehsan Zhian Tabasy and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2015 with categories.
As the data rates of wireline communication links increases, channel impairments such as skin effect, dielectric loss, fiber dispersion, reflections and cross-talk become more pronounced. This warrants more interest in analog-to-digital converter (ADC)-based serial link receivers, as they allow for more complex and flexible back-end digital signal processing (DSP) relative to binary or mixed-signal receivers. Utilizing this back-end DSP allows for complex digital equalization and more bandwidth-efficient modulation schemes, while also displaying reduced process/voltage/temperature (PVT) sensitivity. Furthermore, these architectures offer straightforward design translation and can directly leverage the area and power scaling offered by new CMOS technology nodes. However, the power consumption of the ADC front-end and subsequent digital signal processing is a major issue. Embedding partial equalization inside the front-end ADC can potentially result in lowering the complexity of back-end DSP and/or decreasing the ADC resolution requirement, which results in a more energy-effcient receiver. This dissertation presents efficient implementations for multi-GS/s time-interleaved ADCs with partial embedded equalization. First prototype details a 6b 1.6GS/s ADC with a novel embedded redundant-cycle 1-tap DFE structure in 90nm CMOS. The other two prototypes explain more complex 6b 10GS/s ADCs with efficiently embedded feed-forward equalization (FFE) and decision feedback equalization (DFE) in 65nm CMOS. Leveraging a time-interleaved successive approximation ADC architecture, new structures for embedded DFE and FFE are proposed with low power/area overhead. Measurement results over FR4 channels verify the effectiveness of proposed embedded equalization schemes. The comparison of fabricated prototypes against state-of-the-art general-purpose ADCs at similar speed/resolution range shows comparable performances, while the proposed architectures include embedded equalization as well. The electronic version of this dissertation is accessible from http://hdl.handle.net/1969.1/155223