Design Of High Speed Time Interleaved Delta Sigma D A Converters
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Design Of High Speed Time Interleaved Delta Sigma D A Converters
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Author : Ameya Bhide
language : en
Publisher: Linköping University Electronic Press
Release Date : 2015-08-19
Design Of High Speed Time Interleaved Delta Sigma D A Converters written by Ameya Bhide and has been published by Linköping University Electronic Press this book supported file pdf, txt, epub, kindle and other format this book has been release on 2015-08-19 with Analog-to-digital converters categories.
Digital-to-analog (D/A) converters (or DACs) are one the fundamental building blocks of wireless transmitters. In order to support the increasing demand for highdata-ate communication, a large bandwidth is required from the DAC. With the advances in CMOS scaling, there is an increasing trend of moving a large part of the transceiver functionality to the digital domain in order to reduce the analog complexity and allow easy reconguration for multiple radio standards. ?? DACs can t very well into this trend of digital architectures as they contain a large digital signal processing component and oer two advantages over the traditionally used Nyquist DACs. Firstly, the number of DAC unit current cells is reduced which relaxes their matching and output impedance requirements and secondly, the reconstruction lter order is reduced. Achieving a large bandwidth from ?? DACs requires a very high operating frequency of many-GHz from the digital blocks due to the oversampling involved. This can be very challenging to achieve using conventional ?? DAC architectures, even in nanometer CMOS processes. Time-interleaved ?? (TIDSM) DACs have the potential of improving the bandwidth and sampling rate by relaxing the speed of the individual channels. However, they have received only some attention over the past decade and very few previous works been reported on this topic. Hence, the aim of this dissertation is to investigate architectural and circuit techniques that can further enhance the bandwidth and sampling rate of TIDSM DACs. The rst work is an 8-GS/s interleaved ?? DAC prototype IC with 200-MHz bandwidth implemented in 65-nm CMOS. The high sampling rate is achieved by a two-channel interleaved MASH 1-1 digital ?? modulator with 3-bit output, resulting in a highly digital DAC with only seven current cells. Two-channel interleaving allows the use of a single clock for both the logic and the nal multiplexing. This requires each channel to operate at half the sampling rate i.e. 4 GHz. This is enabled by a high-speed pipelined MASH structure with robust static logic. Measurement results from the prototype show that the DAC achieves 200-MHz bandwidth, –57-dBc IM3 and 26-dB SNDR, with a power consumption of 68-mW at 1-V digital and 1.2-V analog supplies. This architecture shows good potential for use in the transmitter baseband. While a good linearity is obtained from this DAC, the SNDR is found to be limited by the testing setup for sending high-speed digital data into the prototype. The performance of a two-channel interleaved ?? DAC is found to be very sensitive to the duty-cycle of the half-rate clock. The second work analyzes this eect mathematically and presents a new closed-form expression for the SNDR loss of two-channel DACs due to the duty cycle error (DCE) for a noise transfer function (NTF) of (1 — z—1)n. It is shown that a low-order FIR lter after the modulator helps to mitigate this problem. A closed-form expression for the SNDR loss in the presence of this lter is also developed. These expressions are useful for choosing a suitable modulator and lter order for an interleaved ?? DAC in the early stage of the design process. A comparison between the FIR lter and compensation techniques for DCE mitigation is also presented. The nal work is a 11 GS/s 1.1 GHz bandwidth time-interleaved DAC prototype IC in 65-nm CMOS for the 60-GHz radio baseband. The high sampling rate is again achieved by using a two-channel interleaved MASH 1-1 architecture with a 4-bit output i.e only fteen analog current cells. The single clock architecture for the logic and the multiplexing requires each channel to operate at 5.5 GHz. To enable this, a new look-ahead technique is proposed that decouples the two channels within the modulator feedback path thereby improving the speed as compared to conventional loop-unrolling. Full speed DAC testing is enabled by an on-chip 1 Kb memory whose read path also operates at 5.5 GHz. Measurement results from the prototype show that the ?? DAC achieves >53 dB SFDR, < —49 dBc IM3 and 39 dB SNDR within a 1.1 GHz bandwidth while consuming 117 mW from 1 V digital/1.2 V analog supplies. The proposed ?? DAC can satisfy the spectral mask of the 60-GHz radio IEEE 802.11ad WiGig standard with a second order reconstruction lter.
Design Of High Speed Communication Circuits
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Author : Ramesh Harjani
language : en
Publisher: World Scientific
Release Date : 2006-01-17
Design Of High Speed Communication Circuits written by Ramesh Harjani and has been published by World Scientific this book supported file pdf, txt, epub, kindle and other format this book has been release on 2006-01-17 with Technology & Engineering categories.
MOS technology has rapidly become the de facto standard for mixed-signal integrated circuit design due to the high levels of integration possible as device geometries shrink to nanometer scales. The reduction in feature size means that the number of transistor and clock speeds have increased significantly. In fact, current day microprocessors contain hundreds of millions of transistors operating at multiple gigahertz. Furthermore, this reduction in feature size also has a significant impact on mixed-signal circuits. Due to the higher levels of integration, the majority of ASICs possesses some analog components. It has now become nearly mandatory to integrate both analog and digital circuits on the same substrate due to cost and power constraints. This book presents some of the newer problems and opportunities offered by the small device geometries and the high levels of integration that is now possible.The aim of this book is to summarize some of the most critical aspects of high-speed analog/RF communications circuits. Attention is focused on the impact of scaling, substrate noise, data converters, RF and wireless communication circuits and wireline communication circuits, including high-speed I/O.
Energy Efficient Implementation Of Communication Algorithms Through Complexity Reduction
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Author : Narges Mohammadi Sarband
language : en
Publisher: Linköping University Electronic Press
Release Date : 2024-12-13
Energy Efficient Implementation Of Communication Algorithms Through Complexity Reduction written by Narges Mohammadi Sarband and has been published by Linköping University Electronic Press this book supported file pdf, txt, epub, kindle and other format this book has been release on 2024-12-13 with categories.
Energy-efficient implementations are essential for the future and modern society, especially in digital signal processing (DSP) and communication systems, where the rapid growth of devices, such as those battery-driven internet of things (IoT) sensors, necessitates low-complexity and low-power solutions. This thesis concentrates on two areas: constant multiplication and active user detection in wire-less networks. Constant multiplication can be implemented using a shift-and-add (SHA) network. Typically, the number of adders/subtracters is minimized, but the number of cascaded adders/subtracters (depth) also impacts the power consumption. The two classes of algorithms used to solve the problem are adder graph algorithms or sub-expression sharing algorithms. Adder graph algorithms typically yield better results for a single or a low number of inputs, since they do not depend on the representation of the numbers involved. However, they can lead to very high run times and worse results when the number of inputs is high. At the same time, it is known that it is possible to transpose the problem. For example, a sum of products (many inputs) can be transposed to a single input with multiple coefficients, meaning that it is possible to transpose the problem to the more advantageous form, solve it and then transpose the solution back. However, there has been no systematic algorithm available to obtain the transposed result that takes depth into account. In this thesis, a systematic algorithm that obtains the minimum depth of the transposed SHA network subject to the input is introduced. The practical application of the constant multiplication problem is demonstrated through the implementation of a reconfigurable lowpass equalizer, widely used in communication systems and DSP. Various formulations of the constant multiplication problem, combined with pipelining, are explored to identify the most efficient implementation in a 28 nm FD-SOI standard cell, significantly reducing power consumption and highlighting the real-world impact of our research. The second research focuses on the challenge of detecting active users in massive machine-type communication (mMTC) scenarios involving large numbers of devices. The problem is addressed using a pilot-hopping sequence method and is formulated as a non-negative least-squares (NNLS) problem. This work implements two NNLS algorithms, fast projected gradient (Fast) and multiplicative updates (Mult), to solve the active user detection problem. These implementations are implemented in a 28 nm FD-SOI process and are optimized for energy efficiency, chip area, and detection speed. The results demonstrate the ability to perform over a million detections per second with significantly lower energy consumption compared to existing methods. However, the implementations lack reconfigurability, and it can be argued whether the high detection rates are relevant for current practical applications. To enhance practicality and reconfigurability, the Fast algorithm is implemented using a reconfigurable time-multiplexed architecture, reducing resources by reusing them within one iteration. This architecture employs a novel user re-ordering method to enable parallel memory access and continuous operation for successive iterations, thereby increasing the execution speed. The architecture is implemented on numerous FPGA families, demonstrating resource efficiency and reconfigurability by storing the pilot-hopping sequences in memory, while obtaining a more practically usable detection rate of about one to a few thousand detections per second depending on the FPGA family. Energieffektiva implementationer är avgörande för framtiden och det moderna samhället, särskilt inom digital signalbehandling (DSP) och kommunikationssystem, där den snabba tillväxten av enheter, såsom de inom Internet of Things (IoT), kräver lösningar med låg komplexitet och låg effektförbrukning. Denna avhandling fokuserar på två områden: konstantmultiplikation och detektering av aktiva användare i trådlösa nätverk. Konstantmultiplikation kan implementeras med ett shift-and-add (SHA) nätverk. Vanligtvis så minimeras antalet adderare/subtraherare, men antalet kaskadkopplade adderare/subtraherare (djupet) påverkar också effektförbrukningen. De två klasserna av algoritmer för att lösa konstaktmultiplikation baseras på adderargrafer eller gemensamma deluttryck. Addergrafer är oftast bättre vid en eller få ingångar, eftersom de inte beror på vilken representation som talen uttrycks med. För många ingångar så kan beräkningstiden öka väldigt snabbt samt att resultaten ofta är sämre eftersom sökrymden ökar fort. Samtidigt så är det välkänt att det får att transponera problemet. Till exempel så kan en summa produkter (många ingångar) transponeras till en ingång som multipliceras med många olika konstanter. Detta leder till att det är möjligt att transponera problemet till den mest fördelaktiga formen, lösa det och sedan transponera lösningen. Det har tidigare inte funnits någon systematisk algoritm för att transponera ett nätverk som tar hänsyn till djupet, men i denna avhandling så presenteras en som garanterar minimalt djup givet en viss adderargraf som argument. Den praktiska tillämpningen av konstantmultiplikation demonstreras genom implementering av en konfigurerbar lågpassutjämnare, som är allmänt använd i DSP- och kommunikationssystem. Olika formuleringar av konstantmultiplikationsproblemet, kombinerat med pipelining, utforskas för att identifiera den mest effektiva implementationen i en 28 nm FD-SOI-standardcell, vilket avsevärt minskar strömförbrukningen och visar den verkliga påverkan av vår forskning. Den andra forskningen fokuserar på utmaningen att detektera aktiva användare i massive machinetype communication (mMTC) med ett stort antal enheter. Problemet hanteras med hjälp av en pilothoppingssekvensmetod och formuleras som ett problem med non-negative least-squares (NNLS). Detta arbete implementerar två NNLS-algoritmer, fast projected gradient (Fast) och multiplikativa uppdateringar (Mult), för att lösa problemet med detektering av aktiva användare. Dessa implementationer implementerade i en 28 nm FD-SOI-process och är optimerade för energieffektivitet, chiparea och detekteringshastighet. Resultaten visar att mer än en miljon detektioner per sekund kan utföras med betydligt lägre energiförbrukning än befintliga metoder, till stor del för att en iteration beräknas helt parallelt. Dock saknas möjlighet att ändra användarsekvenser och det kan diskuteras om den höga detektionstakten är praktiskt användbar. För att öka praktiskheten implementeras Fast-algoritmen med en konfigurerbar tidsmultiplexad arkitektur, vilken sparar resurser genom att återanvända dem i en iteration. Denna arkitektur använder en ny metod att ordna om användarna för att möjliggöra parallell minnesåtkomst och kontinuerliga beräkning-ar för efterföljande iterationer, vilket ökar exekveringshastigheten. Arkitekturen implementeras på olika FPGA-familjer och visar resurseffektivitet och konfigurerbarhet genom att pilothoppningssekvenserna sparas i minne, samtidigt som en mer praktiskt användbar detektionshastighet från ungefär ett tusen till några tusen detektioner per sekund beroende på FPGA-familj.
High Performance Ad And Da Converters Ic Design In Scaled Technologies And Time Domain Signal Processing
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Author : Pieter Harpe
language : en
Publisher: Springer
Release Date : 2014-07-23
High Performance Ad And Da Converters Ic Design In Scaled Technologies And Time Domain Signal Processing written by Pieter Harpe and has been published by Springer this book supported file pdf, txt, epub, kindle and other format this book has been release on 2014-07-23 with Technology & Engineering categories.
This book is based on the 18 tutorials presented during the 23rd workshop on Advances in Analog Circuit Design. Expert designers present readers with information about a variety of topics at the frontier of analog circuit design, serving as a valuable reference to the state-of-the-art, for anyone involved in analog circuit research and development.
Sigma Delta Converters Practical Design Guide
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Author : Jose M. de la Rosa
language : en
Publisher: John Wiley & Sons
Release Date : 2018-11-05
Sigma Delta Converters Practical Design Guide written by Jose M. de la Rosa and has been published by John Wiley & Sons this book supported file pdf, txt, epub, kindle and other format this book has been release on 2018-11-05 with Technology & Engineering categories.
Thoroughly revised and expanded to help readers systematically increase their knowledge and insight about Sigma-Delta Modulators Sigma-Delta Modulators (SDMs) have become one of the best choices for the implementation of analog/digital interfaces of electronic systems integrated in CMOS technologies. Compared to other kinds of Analog-to-Digital Converters (ADCs), Σ∆Ms cover one of the widest conversion regions of the resolution-versus-bandwidth plane, being the most efficient solution to digitize signals in an increasingly number of applications, which span from high-resolution low-bandwidth digital audio, sensor interfaces, and instrumentation, to ultra-low power biomedical systems and medium-resolution broadband wireless communications. Following the spirit of its first edition, Sigma-Delta Converters: Practical Design Guide, 2nd Edition takes a comprehensive look at SDMs, their diverse types of architectures, circuit techniques, analysis synthesis methods, and CAD tools, as well as their practical design considerations. It compiles and updates the current research reported on the topic, and explains the multiple trade-offs involved in the whole design flow of Sigma-Delta Modulators—from specifications to chip implementation and characterization. The book follows a top-down approach in order to provide readers with the necessary understanding about recent advances, trends, and challenges in state-of-the-art Σ∆Ms. It makes more emphasis on two key points, which were not treated so deeply in the first edition: It includes a more detailed explanation of Σ∆Ms implemented using Continuous-Time (CT) circuits, going from system-level synthesis to practical circuit limitations. It provides more practical case studies and applications, as well as a deeper description of the synthesis methodologies and CAD tools employed in the design of Σ∆ converters. Sigma-Delta Converters: Practical Design Guide, 2nd Edition serves as an excellent textbook for undergraduate and graduate students in electrical engineering as well as design engineers working on SD data-converters, who are looking for a uniform and self-contained reference in this hot topic. With this goal in mind, and based on the feedback received from readers, the contents have been revised and structured to make this new edition a unique monograph written in a didactical, pedagogical, and intuitive style.
Design Of Very High Frequency Multirate Switched Capacitor Circuits
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Author : Seng-Pan U
language : en
Publisher: Springer Science & Business Media
Release Date : 2006
Design Of Very High Frequency Multirate Switched Capacitor Circuits written by Seng-Pan U and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2006 with Computers categories.
Design of Very High-Frequency Multirate Switched-Capacitor Circuits presents the theory and the corresponding CMOS implementation of the novel multirate sampled-data analog interpolation technique which has its great potential on very high-frequency analog frond-end filtering due to its inherent dual advantage of reducing the speed of data-converters and DSP core together with the specification relaxation of the post continuous-time filtering. This technique completely eliminates the traditional phenomenon of sampled-and-hold frequency-shaping at the lower input sampling rate. Also, in order to tackle physical IC imperfections at very high frequency, the state-of-the-art circuit design and layout techniques for high-speed Switched-Capacitor (SC) circuits are comprehensively discussed: -Optimum circuit architecture tradeoff analysis -Simple speed and power trade-off analysis of active elements -High-order filtering response accuracy with respect to capacitor-ratio mismatches -Time-interleaved effect with respect to gain and offset mismatch -Time-interleaved effect with respect to timing-skew and random jitter with non-uniformly holding -Stage noise analysis and allocation scheme -Substrate and supply noise reduction -Gain-and offset-compensation techniques -High-bandwidth low-power amplifier design and layout -Very low timing-skew multiphase generation Two tailor-made optimum design examples in CMOS are presented. The first one achieves a 3-stage 8-fold SC interpolating filter with 5.5MHz bandwidth and 108MHz output sampling rate for a NTSC/PAL CCIR 601 digital video at 3 V. Another is a 15-tap 57MHz SC FIR bandpass interpolating filter with 4-fold sampling rate increase to 320MHz and the first-time embedded frequency band up-translation for DDFS system at 2.5V. The corresponding chip prototype achieves so far the highest operating frequency, highest filter order and highest center frequency with highest dynamic range under the lowest supply voltage when compared to the previously reported high-frequency SC filters in CMOS.
Cmos Telecom Data Converters
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Author : Angel Rodríguez-Vázquez
language : en
Publisher: Springer Science & Business Media
Release Date : 2013-03-09
Cmos Telecom Data Converters written by Angel Rodríguez-Vázquez and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2013-03-09 with Technology & Engineering categories.
CMOS Telecom Data Converters compiles the latest achievements regarding the design of high-speed and high-resolution data converters in deep submicron CMOS technologies. The four types of analog-to-digital converter architectures commonly found in this arena are covered, namely sigma-delta, pipeline, folding/interpolating and flash. For all these types, latest achievements regarding the solution of critical architectural and circuital issues are presented, and illustrated through IC prototypes with measured state-of-the-art performances. Some of these prototypes are conceived to be employed at the chipset of newest generation wireline modems (ADSL and ADSL+). Others are intended for wireless transceivers. Besides analog-to-digital converters, the book also covers other functions needed for communication systems, such as digital-to-analog converters, analog filters, programmable gain amplifiers, digital filters, and line drivers.
Cmos Cascade Sigma Delta Modulators For Sensors And Telecom
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Author : Rocío Río Fernández
language : en
Publisher: Springer Science & Business Media
Release Date : 2006-09-03
Cmos Cascade Sigma Delta Modulators For Sensors And Telecom written by Rocío Río Fernández and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2006-09-03 with Technology & Engineering categories.
Institutional book, not really for bookstore catalogue The book contains valuable information structured to provide insight on how to design SC sigma-delta modulators. It presents architectures, circuits, models, methods and practical considerations for the design of high-performance low-pass switched-capacitor (SC) sigma-delta A/D interfaces for mixed-signal CMOS ASICs. The main focus of the book is on cascade architectures. It differs from other books in the complete, in-depth coverage of SC circuit errors.
Signal Processing Techniques For Power Efficient Wireless Communication Systems
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Author : Fernando Gregorio
language : en
Publisher: Springer Nature
Release Date : 2019-11-23
Signal Processing Techniques For Power Efficient Wireless Communication Systems written by Fernando Gregorio and has been published by Springer Nature this book supported file pdf, txt, epub, kindle and other format this book has been release on 2019-11-23 with Technology & Engineering categories.
This book presents a synthesis of the research carried out in the Laboratory of Signal Processing and Communications (LaPSyC), CONICET, Universidad Nacional del Sur, Argentina, since 2003. It presents models and techniques widely used by the signal processing community, focusing on low-complexity methodologies that are scalable to different applications. It also highlights measures of the performance and impact of each compensation technique. The book is divided into three parts: 1) basic models 2) compensation techniques and 3) applications in advanced technologies. The first part addresses basic architectures of transceivers, their component blocks and modulation techniques. It also describes the performance to be taken into account, regardless of the distortions that need to be compensated. In the second part, several schemes of compensation and/or reduction of imperfections are explored, including linearization of power amplifiers, compensation of the characteristics of analog-to- digital converters and CFO compensation for OFDM modulation. The third and last part demonstrates the use of some of these techniques in modern wireless-communication systems, such as full-duplex transmission, massive MIMO schemes and Internet of Things applications.
Machine Learning Based Design And Optimization Of High Speed Circuits
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Author : Vazgen Melikyan
language : en
Publisher: Springer Nature
Release Date : 2023-12-30
Machine Learning Based Design And Optimization Of High Speed Circuits written by Vazgen Melikyan and has been published by Springer Nature this book supported file pdf, txt, epub, kindle and other format this book has been release on 2023-12-30 with Computers categories.
This book describes machine learning-based new principles, methods of design and optimization of high-speed integrated circuits, included in one electronic system, which can exchange information between each other up to 128/256/512 Gbps speed. The efficiency of methods has been proven and is described on the examples of practical designs. This will enable readers to use them in similar electronic system designs. The author demonstrates newly developed principles and methods to accelerate communication between ICs, working in non-standard operating conditions, considering signal deviation compensation with linearity self-calibration. The observed circuit types also include but are not limited to mixed-signal, high performance heterogeneous integrated circuits as well as digital cores.