High Performance And High Speed Pipelined Adcs
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High Performance And High Speed Pipelined Adcs
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Author : Manar El-Chammas
language : en
Publisher: Springer Nature
Release Date : 2023-05-19
High Performance And High Speed Pipelined Adcs written by Manar El-Chammas and has been published by Springer Nature this book supported file pdf, txt, epub, kindle and other format this book has been release on 2023-05-19 with Technology & Engineering categories.
This book discusses the theoretical foundations and design techniques needed to effectively design high-speed (multi-GS/s) and high-performance pipelined ADCs, which play a critical role in the signal chain of various systems. Readers will be walked through the design and analysis of pipelined ADCs and their topologies, and will learn both theoretical and practical design details that will enable them to explore and build these data converters. The author also presents details on various aspects of pipelined ADCs and their impact on the ADC speed and performance, with a focus on the input buffer and sampling network, the reference amplifier, comparators and their impact on ADC error rate and high-frequency performance, and mismatch estimation and correction.
Dynamic Amplifiers For High Speed Pipelined A D Conversion
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Author : Luan Minh Nguyen
language : en
Publisher:
Release Date : 2012
Dynamic Amplifiers For High Speed Pipelined A D Conversion written by Luan Minh Nguyen and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2012 with categories.
Analog-to-digital converters (ADC) are a vital part of a many applications that require an interface with real-world analog signals. Fueled by the ever increasing demand for higher bandwidth and lower power consumption in many areas, the energy efficiency of ADCs becomes a critical performance criterion. Today, there exist a variety of ADCs that provide high energy efficiency solutions only for low bandwidths (below ~100 MHz). In the high-speed space (above 100 MHz), however, the energy efficiency of ADCs degrades dramatically, and this is especially visible for pipelined ADCs, which take 3-5 times more energy than other architectures that do not emphasize high speed. Furthermore, existing non-pipelined solutions for this bandwidth range are few in numbers, and this presents an opportunity for innovation at both the architectural and circuit design level. This thesis explores a pipelined ADC design that employs a variety of low-power techniques such as dynamic residue amplification and incomplete settling in a unique way to maximize the speed while maintaining low energy (98 fJ/conv-step). The resulting work advances the state-of-the-art by simultaneously achieving a high conversion rate (500 MS/s), low power (5.1 mW), moderate resolution (8 bits), and low input capacitance (55 fF). The experimental converter was implemented in a 65-nm Silicon-on-Insulator (SOI) CMOS process and is among the first high-performance ADCs employing this technology.
Low Power Design Techniques For High Speed Pipelined Adcs
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Author : Naga Sasidhar Lingam
language : en
Publisher:
Release Date : 2009
Low Power Design Techniques For High Speed Pipelined Adcs written by Naga Sasidhar Lingam and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2009 with Low voltage integrated circuits categories.
Real world is analog but the processing of signals can best be done in digital domain. So the need for Analog to Digital Converters (ADCs) is ever rising as more and more applications set in. With the advent of mobile technology, power in electronic equipment is being driven down to get more battery life. Because of their ubiquitous nature, ADCs are prime blocks in the signal chain in which power is intended to be reduced. In this thesis, four techniques to reduce power in high speed pipelined ADCs have been proposed. The first is a capacitor and opamp sharing technique that reduces the load on the first stage opamp by three fold. The second is a capacitor reset technique that aids removing the sample and hold block to reduce power. The third is a modified MDAC which can take rail-to-rail input swing to get an extra bit thus getting rid of a power hungry opamp. The fourth is a hybrid architecture which makes use of an asynchronous SAR ADC as the backend of a pipelined ADC to save power. Measurement and simulation results that prove the efficiency of the proposed techniques are presented.
Systematic Design For Optimisation Of Pipelined Adcs
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Author : João Goes
language : en
Publisher: Springer Science & Business Media
Release Date : 2006-04-18
Systematic Design For Optimisation Of Pipelined Adcs written by João Goes and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2006-04-18 with Technology & Engineering categories.
This excellent reference proposes and develops new strategies, methodologies and tools for designing low-power and low-area CMOS pipelined A/D converters. The task is tackled by following a scientifically-consistent approach. The book may also be used as a text for advanced reading on the subject.
Pipelined Adc Design And Enhancement Techniques
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Author : Imran Ahmed
language : en
Publisher: Springer Science & Business Media
Release Date : 2010-03-10
Pipelined Adc Design And Enhancement Techniques written by Imran Ahmed and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2010-03-10 with Technology & Engineering categories.
Pipelined ADCs have seen phenomenal improvements in performance over the last few years. As such, when designing a pipelined ADC a clear understanding of the design tradeoffs, and state of the art techniques is required to implement today's high performance low power ADCs.
Pipelined Analog To Digital Conversion Using Class Ab Amplifiers
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Author : Kyung Ryun Kim
language : en
Publisher: Stanford University
Release Date : 2010
Pipelined Analog To Digital Conversion Using Class Ab Amplifiers written by Kyung Ryun Kim and has been published by Stanford University this book supported file pdf, txt, epub, kindle and other format this book has been release on 2010 with categories.
In high-performance pipelined analog-to-digital converters (ADCs), the residue amplifiers dissipate the majority of the overall converter power. Therefore, finding alternatives to the relatively inefficient, conventional class-A circuit realization is an active area of research. One option for improvement is to employ class-AB amplifiers, which can, in principle, provide large drive currents on demand and improve the efficiency of residue amplification. Unfortunately, due to the simultaneous demand for high speed and high gain in pipelined ADCs, the improvements seen in class-AB designs have so far been limited. This dissertation presents the design of an efficient class-AB amplification scheme based on a pseudo-differential, single-stage and cascode-free architecture. Nonlinear errors due to finite DC gain are addressed using a deterministic digital background calibration that measures the circuit imperfections in time intervals between normal conversion cycles of the ADC. As a proof of concept, a 12-bit 30-MS/s pipelined ADC was realized using class-AB amplifiers with the proposed digital calibration. The prototype ADC occupies an active area of 0.36 mm2 in 90-nm CMOS. It dissipates 2.95 mW from a 1.2-V supply and achieves an SNDR of 64.5 dB for inputs near the Nyquist frequency. The corresponding figure of merit is 72 fJ/conversion-step.
Power Efficient High Speed Parallel Sampling Adcs For Broadband Multi Carrier Systems
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Author : Yu Lin
language : en
Publisher: Springer
Release Date : 2015-05-07
Power Efficient High Speed Parallel Sampling Adcs For Broadband Multi Carrier Systems written by Yu Lin and has been published by Springer this book supported file pdf, txt, epub, kindle and other format this book has been release on 2015-05-07 with Technology & Engineering categories.
This book addresses the challenges of designing high performance analog-to-digital converters (ADCs) based on the “smart data converters” concept, which implies context awareness, on-chip intelligence and adaptation. Readers will learn to exploit various information either a-priori or a-posteriori (obtained from devices, signals, applications or the ambient situations, etc.) for circuit and architecture optimization during the design phase or adaptation during operation, to enhance data converters performance, flexibility, robustness and power-efficiency. The authors focus on exploiting the a-priori knowledge of the system/application to develop enhancement techniques for ADCs, with particular emphasis on improving the power efficiency of high-speed and high-resolution ADCs for broadband multi-carrier systems.
Advances In Analog And Rf Ic Design For Wireless Communication Systems
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Author : Michael Elliott
language : en
Publisher: Elsevier Inc. Chapters
Release Date : 2013-05-13
Advances In Analog And Rf Ic Design For Wireless Communication Systems written by Michael Elliott and has been published by Elsevier Inc. Chapters this book supported file pdf, txt, epub, kindle and other format this book has been release on 2013-05-13 with Technology & Engineering categories.
This chapter provides an overview of design techniques and system aspects relevant to the application of high-speed pipelined ADCs in wireless base transceiver stations (BTS). The discussion begins with a derivation of typical ADC specifications for the receive path of a multi-carrier BTS system. Next, we investigate issues pertaining to the interface between the ADC and its driving circuitry, including complications that arise with sample-and-hold-amplifier-less (SHA-less) ADC frontends. Lastly, we summarize recent research results that look into the digital linearization of dynamic nonlinearities at the ADC’s frontend.
High Speed Pipelined Adc Using A Bucket Brigade Front End
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Author : Noam Dolev Geldbard
language : en
Publisher:
Release Date : 2013
High Speed Pipelined Adc Using A Bucket Brigade Front End written by Noam Dolev Geldbard and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2013 with categories.
Advanced wireless technologies, such as LTE and LTE advanced, require low-power, high-speed, and high-resolution analog-to-digital converters (ADCs). At present, only the pipelined ADC architecture is capable of meeting the stringent bandwidth, linearity, and resolution requirements for this application. However, in current products, the power efficiency of this architecture is limited by the use of operational amplifiers as inter-stage gain elements. This research investigates an approach where the critical operational amplifiers are replaced by a pulsed-based bucket brigade amplifier, which achieves voltage gain by redistributing charge form a large sampling capacitor to a small load capacitor. This circuit performs the residue amplification with lower power, but is weakly nonlinear and therefore requires digital linearization. Since the power overhead for digital arithmetic in modern CMOS technologies is low, this approach has the potential to yield large overall power savings. To evaluate this concept, a prototype ADC was implemented in 65-nm CMOS. The converter operates at 200 MS/s, consumes 11.5 mW from a 1-V supply, and occupies 0.26 mm2. It achieves an SNDR of 65 dB at low input frequencies and 57.6 dB near Nyquist, which corresponds to an SNDR-based Schreier FOM of 164.5 dB and 157 dB, respectively. These results validate the concept of the proposed pulse-based bucket brigade amplification, and the achieved performance compares favorably with the state of the art.
A High Performance Zero Crossing Based Pipelined Analog To Digital Converter
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Author : Yue Jack Chu
language : en
Publisher:
Release Date : 2008
A High Performance Zero Crossing Based Pipelined Analog To Digital Converter written by Yue Jack Chu and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2008 with categories.
In this thesis, I describe a zero-crossing based pipelined ADC. Unlike traditional pipelined ADCs, this work does not use any op-amps in the signal path. The use of zero-crossing based circuits made it possible to achieve a much better figure of merit. The ADC is design to operate at 200MS/s with a resolution of 12 bits. The simulated results suggest that the target performance is achievable with less than 10 mW of power. This design's figure of merit is at least an order of magnitude better than any existing designs that have comparable speed and accuracy performance. The design will be fabricated later to be tested in silicon.