Highly Linearized Cmos Distributed Bidirectional Amplifier With Cross Coupled Compensator For Wireless Communications
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Distributed Cmos Bidirectional Amplifiers
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Author : Ziad El-Khatib
language : en
Publisher: Springer Science & Business Media
Release Date : 2012-05-02
Distributed Cmos Bidirectional Amplifiers written by Ziad El-Khatib and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2012-05-02 with Technology & Engineering categories.
This book describes methods to design distributed amplifiers useful for performing circuit functions such as duplexing, paraphrase amplification, phase shifting power splitting and power combiner applications. A CMOS bidirectional distributed amplifier is presented that combines for the first time device-level with circuit-level linearization, suppressing the third-order intermodulation distortion. It is implemented in 0.13um RF CMOS technology for use in highly-linear, low-cost UWB Radio-over-Fiber communication systems.
Highly Linearized Cmos Distributed Bidirectional Amplifier With Cross Coupled Compensator For Wireless Communications
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Author : Ziad El-Khatib
language : en
Publisher:
Release Date : 2012
Highly Linearized Cmos Distributed Bidirectional Amplifier With Cross Coupled Compensator For Wireless Communications written by Ziad El-Khatib and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2012 with Electrical engineering categories.
Highly Efficient Linear Cmos Power Amplifiers For Wireless Communications
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Author : Ham Hee Jeon
language : en
Publisher:
Release Date : 2012
Highly Efficient Linear Cmos Power Amplifiers For Wireless Communications written by Ham Hee Jeon and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2012 with Amplifiers (Electronics) categories.
The rapidly expanding wireless market requires low cost, high integration and high performance of wireless communication systems. CMOS technology provides benefits of cost effectiveness and higher levels of integration. However, the design of highly efficient linear CMOS power amplifier that meets the requirement of advanced communication standards is a challenging task because of the inherent difficulties in CMOS technology. The objective of this research is to realize PAs for wireless communication systems that overcoming the drawbacks of CMOS process, and to develop design approaches that satisfying the demands of the industry. In this dissertation, a cascode bias technique is proposed for improving linearity and reliability of the multi-stage cascode CMOS PA. In addition, to achieve load variation immunity characteristic and to enhance matching and stability, a fully-integrated balanced PA is implemented in a 0.18-m CMOS process. A triple-mode balanced PA using switched quadrature coupler is also proposed, and this work saved a large amount of quiescent current and further improved the efficiency in the back-off power. For the low losses and a high quality factor of passive output combining, a transformer-based quadrature coupler was implemented using integrated passive device (IPD) process. Various practical approaches for linear CMOS PA are suggested with the verified results, and they demonstrate the potential PA design approach for WCDMA applications using a standard CMOS technology.
Design Of Cmos Distributed Amplifiers For Broadband Wireline And Wireless Communication Applications
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Author : Kambiz Khodayari Moez
language : en
Publisher:
Release Date : 2006
Design Of Cmos Distributed Amplifiers For Broadband Wireline And Wireless Communication Applications written by Kambiz Khodayari Moez and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2006 with categories.
While the RF building blocks of narrowband system-on-chip designs have increasingly been created in CMOS during the past decade, researchers have started to look at the possibility of implementation of broadband transceivers in CMOS technology. High speed optical links with operating frequencies of up to 40 GHz and ultra wideband (UWB) wireless systems operating in 3 to 10 GHz frequency band are examples of these broadband applications. CMOS offers a low fabrication cost, and a higher level of integration compared with compound semiconductor technologies that currently claim broadband RFIC applications. In this work, we focus on the design of broadband low-noise amplifiers: the fundamental building blocks of high data rate wireline and wireless telecommunication systems. A well established microwave engineering technique - distributed amplification - with a potential bandwidth up to the cut-off frequency of transistors is employed. However, the implementation of distributed amplifiers in CMOS imposes new challenges, such as gain attenuation because of substrate loss of on-chip inductors, a typical large die area, and a large noise-figure. These problems have been addressed in this dissertation as described below. On-chip inductors, the essential components of the distributed amplifiers' gate and drain transmission lines, dissipate more and more power in silicon substrates as well as in metal lines as frequency increases, which in turn reduces the gain and deteriorates the input/output matching. Using active negative resistors implemented by a capacitively source degenerated configuration, we have fully compensated the loss of the transmission lines in order to achieve a flat gain of 10 dB over the entire DC-to-44 GHz bandwidth. We have addressed another drawback of distributed amplifiers, large die area, by utilizing closely-placed RF transmission lines instead of spiral inductors. Because of a more compact implementation of transmission lines, the area of the distributed amplifiers is considerably reduced at the expense of extra design steps required for the modeling of the closely-placed RF transmission lines. A post-layout simulation method is developed to take into account the effect of inductive and capacitive coupling by incorporating a 3D EM simulator into the design process. A 9-dB 27-GHz distributed amplifier has been fabricated in an area as small as 0.17 mm2 using 180nm TSMC's CMOS process. For wireless applications (UWB), a very low-noise figure is required for the broadband preamplifier. Conventional distributed amplifiers fail to provide a low noise figure mainly because of the noise injected by the terminating resistor of the gate transmission lines. We have replaced the terminating resistor with a frequency-dependent resistor which trades off the low frequency input matching of the distributed amplifier (not required for UWB) with a better noise performance. Our proposed design provides a gain of 12 dB with an average noise figure of 3.4 dB over the entire 3-10 GHz band, advancing the state-of-the-art implementation of broadband LNAs.
Cmos Polar Digital Power Amplifier For High Data Rate Wireless Communications
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Author : Qiuyao Zhu
language : en
Publisher:
Release Date : 2016
Cmos Polar Digital Power Amplifier For High Data Rate Wireless Communications written by Qiuyao Zhu and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2016 with categories.
Cmos Power Amplifiers For Wireless Communications
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Author : Chengzhou Wang
language : en
Publisher:
Release Date : 2003
Cmos Power Amplifiers For Wireless Communications written by Chengzhou Wang and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2003 with categories.
High Efficiency Switching Cmos Power Amplifiers For Wireless Communications
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Author : Ockgoo Lee
language : en
Publisher:
Release Date : 2009
High Efficiency Switching Cmos Power Amplifiers For Wireless Communications written by Ockgoo Lee and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2009 with Amplifiers (Electronics) categories.
High-efficiency performance is one of the most important requirements of power : amplifiers (PAs) for wireless applications. However, the design of highly efficient CMOS.
High Power Linear Cmos Power Amplifier For Wlan Applications
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Author : Ali Afsahi
language : en
Publisher:
Release Date : 2013
High Power Linear Cmos Power Amplifier For Wlan Applications written by Ali Afsahi and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2013 with categories.
The advancement of CMOS technology has enabled a high level of integration in modern, low cost, small form-factor and low power wireless devices. While power amplifiers (PAs) are key components in wireless transceivers, their realization and integration in standard CMOS technology has shown several challenges. The modern wireless standards such as WLAN and LTE, utilize higher order modulation schemes in order to increase the data rate and efficiently use the limited available spectrum and also provide a robust link in a fading environment. These modulations possess a very high peak-to-average ratio (PAR) and require a very linear power amplifier to preserve the integrity of the signal. In this dissertation several linearization and power combining techniques have been proposed to address the challenges of designing a high power and linear PA in CMOS for WLAN applications. To demonstrate these techniques in silicon, three chips have been designed and fabricated in 65nm standard CMOS. In the first chip, a fully integrated dual-band power amplifiers with on-chip baluns for 802.11n MIMO WLAN applications are implemented. With a 3.3v supply, the PAs produce a saturated output power of 28.3dBm and 26.7dBm with peak drain efficiency of 35.3% and 25.3% for the 2.4GHz and 5GHz bands, respectively. By utilizing multiple fully self-contained linearization algorithms, an EVM of -25dB is achieved at 22.4dBm for the 2.4GHz band and 20.5dBm for the 5GHz band while transmitting 54Mbs OFDM. In the next two designs, two monolithic power combining schemes for CMOS power amplifiers, distributed-LC and current-mode transformer-based, are compared. Fully integrated 2.4GHz power amplifiers (PAs) using these techniques were fabricated. From a 3.3 V supply, the distributed-LC combined PA produces a saturated power of 31.5dBm with peak PAE of 25%. The current-mode transformer based PA combiner produces 33.5dBm saturated power with 37.6% peak PAE. With gm-linearization and digital pre-distortion, these PAs transmit 25.5dBm and 26.4dBm with -25dB EVM for a 54Mb/s OFDM signal respectively.
Cmos Rf Power Amplifier Design Approaches For Wireless Communications
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Author : Sataporn Pornpromlikit
language : en
Publisher:
Release Date : 2010
Cmos Rf Power Amplifier Design Approaches For Wireless Communications written by Sataporn Pornpromlikit and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2010 with categories.
This dissertation focuses on the design of CMOS power amplifiers for modern wireless handsets, where stringent linearity requirements and high power efficiency are difficult to achieve simultaneously. CMOS technology has been an attractive technology for research in fully-integrated transceivers due to its low cost and high-integration capability, as well as its continuously improving high-frequency performance. Its advantages, however, come at the cost of continuously reduced breakdown voltages, low isolation and high power loss in the substrate. To address these limitations, a stacked-FET design technique is first developed to systematically divide the voltage stress among several transistors connected in series, allowing the use of a larger supply voltage. The voltage swing of each stacked device is added in phase to provide a larger output power to the load without the requirement of a large impedance transformation. To investigate this technique, a fully-integrated 20 dBm RF power amplifier is first implemented using 0.25-[mu]m silicon-on-sapphire MOSFETs. By using triple-stacked FETs, the optimum load impedance for a 20 dBm power amplifier increases to 50 [Omega] so impedance transformation is not required at the output. Measurement of a single-stage linear power amplifier shows a small-signal gain of 17.1 dB and a saturated output power of 21.0 dBm with a power added efficiency (PAE) of 44.0% at 1.88 GHz. With an IS-95 code division multiple access (CDMA) modulated signal, the power amplifier shows average output power of 16.3 dBm and PAE of 18.7% with ACPR below -42 dBc. The concept is then further demonstrated at higher voltage and power level. A single-stage quadruple-stacked-FET linear power amplifier is presented using 0.28-[mu]m 2.5-V standard I/O FETs in a 0.13- & mu;m silicon-on-insulator (SOI) CMOS technology. The PA is designed to withstand up to 9 V of supply voltage before reaching its breakdown limit. The measured PA achieves a small-signal gain of 14.6 dB, a saturated output power of 32.4 dBm, and a PAE of 47% at 1.9 GHz with a 6.5-V supply. Using a reverse-link IS-95 CDMA modulated signal, the PA shows an average output power of up to 28.7 dBm with a PAE of 41.2% while meeting the adjacent channel power ratio requirement. The PA also shows an average output power of up to 29.4 dBm with a PAE of 41.4% while meeting the adjacent channel leakage ratio requirement of an uplink wideband code division multiple access (WCDMA) modulated signal. These performances are comparable to those of GaAs-based power amplifiers. To fully exploit the advantages of higher-speed CMOS technology and the availability of co-integrated digital circuitry, a digital-intensive transceiver architecture is explored as an alternative in the second part of the dissertation. A single-ended digitally-modulated power amplifier (DPA) is demonstrated in a 0.13-[mu]m 1.2-V SOI CMOS technology, to be used in a multi-standard RF polar transmitter. The amplitude modulation is done by digitally controlling the number of activated unit amplifiers whose currents are summed at the output. The DPA is designed for multi-mode multi-band functionality by avoiding frequency-selective components, except for the final-stage output matching network. The measured DPA delivers a 24.9-dBm peak output power at 900 MHz with a maximum power efficiency of 62.7%. Similar high-efficiency performance is also exhibited at 1.92 GHz with a reconfigured matching network. By employing a digital pre-distortion technique, the DPA could meet linearity requirements for both the enhanced data rate for GSM evolution (EDGE) and WCDMA standards.
Frequency Synthesis And Power Amplifiers For Wireless Communication Systems In Cmos
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Author : Stephen Paul Bruss
language : en
Publisher:
Release Date : 2009
Frequency Synthesis And Power Amplifiers For Wireless Communication Systems In Cmos written by Stephen Paul Bruss and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2009 with categories.
As CMOS technology continues to advance to smaller feature sizes, digital-logic circuits use less power while becoming faster and smaller. On the other hand, wireless analog circuits often benefit from the higher speed, but suffer various ill effects making conventional analog circuits difficult to design. Integrating wireless analog functionality onto high-volume CMOS greatly reduces the size and cost of wireless devices, which is motivating a tsunami of engineering innovation. In this work we present three wireless analog functions in CMOS: a linearized varactor, phased-locked loop (PLL), and power-amplifier (PA}. To improve the tuning linearity at the cost of a lower capacitance tuning ratio, many circuits tune a large varactor over a small portion of its tuning range. We demonstrate here that a conventional varactor's performance can be improved by breaking it into smaller, independently tuned, parallel segments. This increased tuning dimensionality can enable a varactor to be realized with a high tuning linearity over most of its tuning range while reducing the capacitance's dependence on the instantaneous radio-frequency input signal. In many applications, PLLs need to have a large fine-tuning frequency range to accommodate environmental drift such as temperature. Typically, the fine-tuning sensitivity of the varactor in a PLL's voltage-controlled oscillator is proportional to its fine-tuning range, which makes the PLL more susceptible to picking up noise and spurs. A new dual-path PLL architecture is introduced that uses a softly switched varactor array in a digitally controlled integral path. This architecture decouples the PLL's tuning sensitivity from its tuning range, thus achieving a very low fine-tuning sensitivity. To realize high spectral efficiency, many wireless schemes modulate both the radio-frequency carrier's phase and envelope, necessitating the use of a linear PA. Hence battery powered wireless transceivers require a PA that is both linear and power efficient, which, over even a modest dynamic range, would be difficult to implement in CMOS. Various PA linearization methods are discussed leading to the chosen polar-feedback method. The designs, implementations and measurements for some key blocks required for a PA with polar feedback are presented and the challenges remaining to implement a working system are discussed.