Low Power Techniques For Successive Approximation Register Sar Analog To Digital Converters
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Low Power Techniques For Successive Approximation Register Sar Analog To Digital Converters
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Author : Ramgopal Sekar
language : en
Publisher:
Release Date : 2010
Low Power Techniques For Successive Approximation Register Sar Analog To Digital Converters written by Ramgopal Sekar and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2010 with categories.
In this work, the author investigated circuit techniques to reduce the power consumption of Successive Approximation Register Analog-to-Digital Converter (SAR-ADC). The author developed four low-power SAR-ADC design techniques, which are: (1) Low-power SAR-ADC design with split voltage reference, (2) Charge recycling techniques for low-power SAR-ADC design, (3) Low-power SAR-ADC design using two-capacitor arrays, (4) Power reduction techniques by dynamically minimizing SAR-ADC conversion cycles. Matlab simulations are performed to investigate the power saving by the proposed techniques. Simulation results show that significant power reduction can be achieved by using the developed techniques. In addition, design issues such as area overhead, design complexity associated with the proposed low-power techniques are also discussed in the thesis.
Charge Sharing Sar Adcs For Low Voltage Low Power Applications
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Author : Taimur Rabuske
language : en
Publisher: Springer
Release Date : 2016-08-02
Charge Sharing Sar Adcs For Low Voltage Low Power Applications written by Taimur Rabuske and has been published by Springer this book supported file pdf, txt, epub, kindle and other format this book has been release on 2016-08-02 with Technology & Engineering categories.
This book introduces readers to the potential of charge-sharing (CS) successive approximation register (SAR) analog-to-digital converters (ADCs), while providing extensive analysis of the factors that limit the performance of the CS topology. The authors present guidelines and useful techniques for mitigating the limitations of the architecture, while focusing on the implementation under restricted power budgets and voltage supplies.
High Speed And Low Power Techniques For Successive Approximation Register Analog To Digital Converters
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Author : Eric Lee Swindlehurst
language : en
Publisher:
Release Date : 2020
High Speed And Low Power Techniques For Successive Approximation Register Analog To Digital Converters written by Eric Lee Swindlehurst and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2020 with categories.
Broadband wireless communication systems demand power-efficient analog-to-digital converters (ADCs) in the GHz and medium resolution regime. While high-speed architectures such as the flash and pipelined ADCs are capable of GHz operations, their high-power consumption reduces their attractiveness for mobile applications. On the other hand, the successive-approximation-register (SAR) ADC has an excellent power efficiency, but its slow speed has traditionally limited it to MHz applications. This dissertation puts forth several novel techniques to significantly increase the speed and power efficiency of the SAR architecture and demonstrates them in a low-power 10-GHz SAR ADC suitable for broadband wireless communications.
Accelerated Successive Approximation Technique For Analog To Digital Converter Design
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Author : Ram Harshvardhan Radhakrishnan
language : en
Publisher:
Release Date : 2015
Accelerated Successive Approximation Technique For Analog To Digital Converter Design written by Ram Harshvardhan Radhakrishnan and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2015 with Analog-to-digital converters categories.
This thesis work presents a novel technique to reduce the number of conversion cycles for Successive Approximation register (SAR) Analog to Digital Converters (ADC), thereby potentially improving the conversion speed as well as reducing its power consumption. Conventional SAR ADCs employ the binary search algorithm and they update only one bound, either the upper or lower bound, of the search space during one conversion cycle. The proposed method, referred to as the Accelerated-SAR or A-SAR, is capable of updating both the lower and upper bounds in a single conversion cycle. Even in cases that it can update only one bound, it does more aggressively. The proposed technique is implemented in a 10-bit SAR ADC circuit with 0.5V power supply and rail-to-rail input range. To cope with the ultra-low voltage design challenge, Time-to-Digital conversion techniques are used in the implementation. Important design issues are also discussed for the charge scaling array and Voltage Controlled Delay Lines (VCDL), which are important building blocks in the ADC implementation.
Comparator Power Reduction For Low Power Successive Approximation Analog To Digital Converters
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Author : Muhammad Ahmadi
language : en
Publisher:
Release Date : 2015
Comparator Power Reduction For Low Power Successive Approximation Analog To Digital Converters written by Muhammad Ahmadi and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2015 with Comparator circuits categories.
Many applications like sensor nodes, wireless communications and consumer products require analog-to-digital converters (ADCs) to digitize the analog information. Charge redistribution successive approximation register (SAR) ADC has been a popular candidate in these applications due to its simplicity, low power consumption, medium speed and resolution. The three primary components of a SAR ADC are the digital-to-analog converter (DAC), digital SAR logic, and comparator. The power consumption of the DAC can be greatly minimized by employing a small unit capacitor and digital circuits benefit from technology scaling. Consequently, the comparator has become a major source of power consumption in recent power efficient SAR ADCs. Two comparator power reduction techniques are proposed which are based on the observation that the comparator noise variance need not be the same for each bit cycle of the SAR ADC. So, the performance of the SAR ADC is analyzed rigorously assuming that the comparator thermal noise differs for each bit cycle. The mathematical model suggests that using the same comparator noise variance for each bit cycle is suboptimal and results in more power consumption than necessary. As a first technique, a noise programmable comparator based on majority vote technique is proposed to adjust the comparator noise performance at each bit step by changing the number of votes taken at each bit step. As a proof of concept, a 10b SAR ADC that operates at 0.5 V supply voltage and supports a flexible differential input dynamic range from 0.4 V to 1 V has been fabricated in 65nm CMOS process. Second, the optimal comparators that need to be used to achieve a desired overall performance at minimum power levels are theoretically analyzed. Simulation results show that up to 50% and 60% reduction in comparator power consumption for 10b and 12b SAR ADCs, respectively, can be achieved. To reduce the implementation complexity, the comparator noise allocation problem is also solved when fewer than N comparators are employed in an N-bit SAR ADC. Simulation results suggest that two comparators are sufficient to achieve near ideal performance.
Principles Of Data Conversion System Design
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Author : Behzad Razavi
language : en
Publisher: Wiley-IEEE Press
Release Date : 1995
Principles Of Data Conversion System Design written by Behzad Razavi and has been published by Wiley-IEEE Press this book supported file pdf, txt, epub, kindle and other format this book has been release on 1995 with Computers categories.
This advanced text and reference covers the design and implementation of integrated circuits for analog-to-digital and digital-to-analog conversion. It begins with basic concepts and systematically leads the reader to advanced topics, describing design issues and techniques at both circuit and system level. Gain a system-level perspective of data conversion units and their trade-offs with this state-of-the art book. Topics covered include: sampling circuits and architectures, D/A and A/D architectures; comparator and op amp design; calibration techniques; testing and characterization; and more!
Design Techniques For Low Power Sar Adcs In Nano Scale Cmos Technologies
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Author : Long Chen (Doctorate in Electrical and Computer engineering)
language : en
Publisher:
Release Date : 2016
Design Techniques For Low Power Sar Adcs In Nano Scale Cmos Technologies written by Long Chen (Doctorate in Electrical and Computer engineering) and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2016 with categories.
This thesis presents low power design techniques for successive approximation register (SAR) analog-to-digital converters (ADCs) in nano-scale CMOS technologies. Low power SAR ADCs face two major challenges especially at high resolutions: (1) increased comparator power to suppress the noise, and (2) increased DAC switching energy due to the large DAC size. To improve the comparator’s power efficiency, a statistical estimation based comparator noise reduction technique is presented. It allows a low power and noisy comparator to achieve high signal-to-noise ratio (SNR) by estimating the conversion residue. A first prototype ADC in 65nm CMOS has been developed to validate the proposed noise reduction technique. It achieves 4.5 fJ/conv-step Walden figure of merit and 64.5 dB signal-to-noise and distortion ratio (SNDR). In addition, a bidirectional single-side switching technique is developed to reduce the DAC switching power. It can reduce the DAC switching power and the total number of unit capacitors by 86% and 75%, respectively. A second prototype ADC with the proposed switching technique is designed and fabricated in 180nm CMOS technology. It achieves an SNDR of 63.4 dB and consumes only 24 Wat 1MS/s, leading to aWalden figure of merit of 19.9 fJ/conv-step. This thesis also presents an improved loop-unrolled SAR ADC, which works at high frequency with reduced SAR logic power and delay. It employs the bidirectional single-side switching technique to reduce the comparator common-mode voltage variation. In addition, it uses a Vcm-adaptive offset calibration technique which can accurately calibrate comparator’s offset at its operating Vcm. A prototype ADC designed in 40nm CMOS achieves 35 dB at 700 MS/s sampling rate and consumes only 0.95 mW, leading to a Walden figure of merit of 30 fJ/conv-step.
Low Power Successive Approximation Analog To Digital Converter With Digital Calibration
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Author : Wei Li
language : en
Publisher:
Release Date : 2014
Low Power Successive Approximation Analog To Digital Converter With Digital Calibration written by Wei Li and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2014 with Successive approximation analog-to-digital converters categories.
IC designers are continuously facing the challenges from reduced CMOS feature sizes and supply voltages. ADCs that deliver satisfactory resolutions/speeds while utilizing the state-of-the-art technologies to save power are in high demand. The analog circuits are more and more assisted by various digital calibration techniques to get boosted performances. This dissertation is focused on a low-power 12-bit 12.5-MS/s successive approximation (SAR) ADC with a couple of calibration schemes. The performances of the proposed SAR ADC are enhanced in two directions. To reduce the power dissipation, a power saving strategy has been proposed. Also, several foreground calibration methods for SAR ADCs have been proposed to reduce power dissipation and enhance conversion accuracy. The design was fabricated in 40nm CMOS technology. Measurement results after calibration showed a SFDR of 82.2 dB, and a THD improvement of 22.5 dB. Finally, two new schemes to realize teraohm on-chip resistance are presented. One of the schemes utilizes a switched-capacitor array, and the other utilizes a switch-capacitor ladder. Using these schemes, large resistances can be fabricated with standard CMOS process in an affordable chip area.
Advances In Analog And Rf Ic Design For Wireless Communication Systems
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Author : Kostas Doris
language : en
Publisher: Elsevier Inc. Chapters
Release Date : 2013-05-13
Advances In Analog And Rf Ic Design For Wireless Communication Systems written by Kostas Doris and has been published by Elsevier Inc. Chapters this book supported file pdf, txt, epub, kindle and other format this book has been release on 2013-05-13 with Technology & Engineering categories.
This paper reviews recent developments of interleaved Successive Approximation Analog-to-Digital converters (SAR) in deep sub-micron CMOS technologies. The discussion covers design tradeoffs and degrees of freedom related to the impact of extensive interleaving with many SAR units on bandwidth, noise, linearity, and spurious performance. The impact of interleaving mismatches on representative broadband and multi-carrier narrowband signals is also discussed. Next, two examples are given demonstrating how interleaving with many ADCs can be transformed from a weakness to a strength. The first example concerns low spurious performance enabled by redundant SAR converters and randomization of their operation. The second example presents spectral sensing techniques.
Data Conversion Handbook
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Author : Walt Kester
language : en
Publisher: Newnes
Release Date : 2005
Data Conversion Handbook written by Walt Kester and has been published by Newnes this book supported file pdf, txt, epub, kindle and other format this book has been release on 2005 with Computers categories.
This complete update of a classic handbook originally created by Analog Devices and never previously published offers the most complete and up-to-date reference available on data conversion, from the world authority on the subject. It describes in depth the theory behind and the practical design of data conversion circuits. It describes the different architectures used in A/D and D/A converters - including many advances that have been made in this technology in recent years - and provides guidelines on which types are best suited for particular applications. It covers error characterization and testing specifications, essential design information that is difficult to find elsewhere. The book also contains a wealth of practical application circuits for interfacing and supporting A/D and D/A converters within an electronic system. In short, everything an electronics engineer needs to know about data converters can be found in this volume, making it an indispensable reference with broad appeal. The accompanying CD-ROM provides software tools for testing and analyzing data converters as well as a searchable pdf version of the text. * brings together a huge amount of information impossible to locate elsewhere. * many recent advances in converter technology simply aren't covered in any other book. * a must-have design reference for any electronics design engineer or technician