Low Power Successive Approximation Analog To Digital Converter With Digital Calibration
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Low Power Successive Approximation Analog To Digital Converter With Digital Calibration
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Author : Wei Li
language : en
Publisher:
Release Date : 2014
Low Power Successive Approximation Analog To Digital Converter With Digital Calibration written by Wei Li and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2014 with Successive approximation analog-to-digital converters categories.
IC designers are continuously facing the challenges from reduced CMOS feature sizes and supply voltages. ADCs that deliver satisfactory resolutions/speeds while utilizing the state-of-the-art technologies to save power are in high demand. The analog circuits are more and more assisted by various digital calibration techniques to get boosted performances. This dissertation is focused on a low-power 12-bit 12.5-MS/s successive approximation (SAR) ADC with a couple of calibration schemes. The performances of the proposed SAR ADC are enhanced in two directions. To reduce the power dissipation, a power saving strategy has been proposed. Also, several foreground calibration methods for SAR ADCs have been proposed to reduce power dissipation and enhance conversion accuracy. The design was fabricated in 40nm CMOS technology. Measurement results after calibration showed a SFDR of 82.2 dB, and a THD improvement of 22.5 dB. Finally, two new schemes to realize teraohm on-chip resistance are presented. One of the schemes utilizes a switched-capacitor array, and the other utilizes a switch-capacitor ladder. Using these schemes, large resistances can be fabricated with standard CMOS process in an affordable chip area.
A 16 Bit 500ksps Low Power Successive Approximation Analog To Digital Converter
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Author : Kun Yang
language : en
Publisher:
Release Date : 2009
A 16 Bit 500ksps Low Power Successive Approximation Analog To Digital Converter written by Kun Yang and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2009 with Analog-to-digital converters categories.
A Study Of Capacitor Array Calibration For A Successive Approximation Analog To Digital Converter
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Author : Ji Ma
language : en
Publisher:
Release Date : 2013
A Study Of Capacitor Array Calibration For A Successive Approximation Analog To Digital Converter written by Ji Ma and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2013 with categories.
Analog-to-digital converters (ADCs) are driven by rapid development of mobile communication systems to have higher speed, higher resolution and lower power consumption. Among multiple ADC architectures, successive approximation (SAR) ADCs attract great attention in mixed-signal design community recently. It is due to the fact that they do not contain amplification components and the digital logics are scaling friendly. Therefore, it is easier to design a SAR ADC with smaller component size in advanced technology than other ADC architectures, which decreases the power consumption and increases the speed of the circuit. However, capacitor mismatch limits the minimum size of unit capacitors which could be used for a SAR ADC with more than 10 bit resolution. Large capacitor both limits conversion speed and increases switching power. In this design project, a novel switching scheme and a novel calibration method are adopted to overcome the capacitor mismatch constraint. The switching scheme uses monotonic switching in a SAR ADC to gain one extra bit, and switches a dummy capacitor between the common mode voltage level (Vcm) and the ground (gnd) to obtain another extra bit. To keep the resolution constant, the capacitor number is reduced by two. The calibration method extracts missing code width to estimate the actual value of capacitors. The missing code extraction is accomplished by detecting metastable state of a comparator, forcing the current bit value and using less significant bits to measure the actual capacitor value. Dither method is adopted to improve calibration accuracy. Behavior model simulation is provided to verify the effectiveness of the calibration method. A circuit design of a 12 bit ADC and the simulation for schematic design is presented in this report.
Ultra Low Voltage Frequency Synthesizer And Successive Approximation Analog To Digital Converter For Biomedical Applications
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Author : Chung-Chih Hung
language : en
Publisher: Springer Nature
Release Date : 2021-12-07
Ultra Low Voltage Frequency Synthesizer And Successive Approximation Analog To Digital Converter For Biomedical Applications written by Chung-Chih Hung and has been published by Springer Nature this book supported file pdf, txt, epub, kindle and other format this book has been release on 2021-12-07 with Technology & Engineering categories.
This book introduces the origin of biomedical signals and the operating principles behind them and introduces the characteristics of common biomedical signals for subsequent signal measurement and judgment. Since biomedical signals are captured by wearable devices, sensor devices, or implanted devices, these devices are all battery-powered to maintain long working time. We hope to reduce their power consumption to extend service life, especially for implantable devices, because battery replacement can only be done through surgery. Therefore, we must understand how to design low-power integrated circuits. Both implantable and in-vitro medical signal detectors require two basic components to collect and transmit biomedical signals: an analog-to-digital converter and a frequency synthesizer because these measured biomedical signals are wirelessly transmitted to the relevant receiving unit. The core unit of wireless transmission is the frequency synthesizer, which provides a wide frequency range and stable frequency to demonstrate the quality and performance of the wireless transmitter. Therefore, the basic operating principle and model of the frequency synthesizer are introduced. We also show design examples and measurement results of a low-power low-voltage integer-N frequency synthesizer for biomedical applications. The detection of biomedical signals needs to be converted into digital signals by an analog-to-digital converter to facilitate subsequent signal processing and recognition. Therefore, the operating principle of the analog-to-digital converter is introduced. We also show implementation examples and measurement results of low-power low-voltage analog-to-digital converters for biomedical applications.
An Implementation Of 1 5 Bits Stage Low Power Successive Approximation Register Analog To Digital Converter By Using On Chip Calibration
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Author :
language : en
Publisher:
Release Date : 2015
An Implementation Of 1 5 Bits Stage Low Power Successive Approximation Register Analog To Digital Converter By Using On Chip Calibration written by and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2015 with categories.
Time Interleaved Analog To Digital Converters
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Author : Simon Louwsma
language : en
Publisher: Springer Science & Business Media
Release Date : 2010-09-08
Time Interleaved Analog To Digital Converters written by Simon Louwsma and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2010-09-08 with Technology & Engineering categories.
Time-interleaved Analog-to-Digital Converters describes the research performed on low-power time-interleaved ADCs. A detailed theoretical analysis is made of the time-interleaved Track & Hold, since it must be capable of handling signals in the GHz range with little distortion, and minimal power consumption. Timing calibration is not attractive, therefore design techniques are presented which do not require timing calibration. The design of power efficient sub-ADCs is addressed with a theoretical analysis of a successive approximation converter and a pipeline converter. It turns out that the first can consume about 10 times less power than the latter, and this conclusion is supported by literature. Time-interleaved Analog-to-Digital Converters describes the design of a high performance time-interleaved ADC, with much attention for practical design aspects, aiming at both industry and research. Measurements show best-inclass performance with a sample-rate of 1.8 GS/s, 7.9 ENOBs and a power efficiency of 1 pJ/conversion-step.
Low Power High Resolution Analog To Digital Converters
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Author : Amir Zjajo
language : en
Publisher: Springer Science & Business Media
Release Date : 2010-10-29
Low Power High Resolution Analog To Digital Converters written by Amir Zjajo and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2010-10-29 with Technology & Engineering categories.
With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. This has recently generated a great demand for low-power, low-voltage A/D converters that can be realized in a mainstream deep-submicron CMOS technology. However, the discrepancies between lithography wavelengths and circuit feature sizes are increasing. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. The inherent randomness of materials used in fabrication at nanoscopic scales means that performance will be increasingly variable, not only from die-to-die but also within each individual die. Parametric variability will be compounded by degradation in nanoscale integrated circuits resulting in instability of parameters over time, eventually leading to the development of faults. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods. In an attempt to address these issues, Low-Power High-Resolution Analog-to-Digital Converters specifically focus on: i) improving the power efficiency for the high-speed, and low spurious spectral A/D conversion performance by exploring the potential of low-voltage analog design and calibration techniques, respectively, and ii) development of circuit techniques and algorithms to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover errors continuously. The feasibility of the described methods has been verified by measurements from the silicon prototypes fabricated in standard 180nm, 90nm and 65nm CMOS technology.
Self Calibration And Digital Trimming Of Successive Approximation Analog To Digital Converters
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Author : Shankar Thirunakkarasu
language : en
Publisher:
Release Date : 2014
Self Calibration And Digital Trimming Of Successive Approximation Analog To Digital Converters written by Shankar Thirunakkarasu and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2014 with Successive approximation analog-to-digital converters categories.
Several state of the art, monitoring and control systems, such as DC motorcontrollers, power line monitoring and protection systems, instrumentation systems and battery monitors require direct digitization of a high voltage input signals. Analog-to-Digital Converters (ADCs) that can digitize high voltage signals require high linearity and low voltage coefficient capacitors. A built in self-calibration and digital-trim algorithm correcting static mismatches in Capacitive Digital-to-Analog Converter (CDAC) used in Successive Approximation Register Analog to Digital Converters (SARADCs) is proposed. The algorithm uses a dynamic error correction (DEC) capacitor to cancel the static errors occurring in each capacitor of the array as the first step upon power-up and eliminates the need for an extra calibration DAC. Self-trimming is performed digitally during normal ADC operation. The algorithm is implemented on a 14-bit high-voltage input range SAR ADC with integrated dynamic error correction capacitors. The IC is fabricated in 0.6-um high voltage compliant CMOS process, accepting up to 24Vpp differential input signal. The proposed approach achieves 73.32 dB Signal to Noise and Distortion Ratio (SNDR) which is an improvement of 12.03 dB after self-calibration at 400 kS/s sampling rate, consuming 90-mW from a +/-15V supply. The calibration circuitry occupies 28% of the capacitor DAC, and consumes less than 15mW during operation. Measurement results shows that this algorithm reduces INL from as high as 7 LSBs down to 1 LSB and it works even in the presence of larger mismatches exceeding 260 LSBs. Similarly, it reduces DNL errors from 10 LSBs down to 1 LSB. The ADC occupies an active area of 9.76 mm2.
Low Power Techniques For Successive Approximation Register Sar Analog To Digital Converters
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Author : Ramgopal Sekar
language : en
Publisher:
Release Date : 2010
Low Power Techniques For Successive Approximation Register Sar Analog To Digital Converters written by Ramgopal Sekar and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2010 with categories.
In this work, the author investigated circuit techniques to reduce the power consumption of Successive Approximation Register Analog-to-Digital Converter (SAR-ADC). The author developed four low-power SAR-ADC design techniques, which are: (1) Low-power SAR-ADC design with split voltage reference, (2) Charge recycling techniques for low-power SAR-ADC design, (3) Low-power SAR-ADC design using two-capacitor arrays, (4) Power reduction techniques by dynamically minimizing SAR-ADC conversion cycles. Matlab simulations are performed to investigate the power saving by the proposed techniques. Simulation results show that significant power reduction can be achieved by using the developed techniques. In addition, design issues such as area overhead, design complexity associated with the proposed low-power techniques are also discussed in the thesis.
Self Calibration Techniques For Successive Approximation Analog To Digital Converters
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Author : Hae-Seung Lee
language : en
Publisher:
Release Date : 1984
Self Calibration Techniques For Successive Approximation Analog To Digital Converters written by Hae-Seung Lee and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 1984 with categories.