Self Calibration And Digital Trimming Of Successive Approximation Analog To Digital Converters
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Self Calibration And Digital Trimming Of Successive Approximation Analog To Digital Converters
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Author : Shankar Thirunakkarasu
language : en
Publisher:
Release Date : 2014
Self Calibration And Digital Trimming Of Successive Approximation Analog To Digital Converters written by Shankar Thirunakkarasu and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2014 with Successive approximation analog-to-digital converters categories.
Several state of the art, monitoring and control systems, such as DC motorcontrollers, power line monitoring and protection systems, instrumentation systems and battery monitors require direct digitization of a high voltage input signals. Analog-to-Digital Converters (ADCs) that can digitize high voltage signals require high linearity and low voltage coefficient capacitors. A built in self-calibration and digital-trim algorithm correcting static mismatches in Capacitive Digital-to-Analog Converter (CDAC) used in Successive Approximation Register Analog to Digital Converters (SARADCs) is proposed. The algorithm uses a dynamic error correction (DEC) capacitor to cancel the static errors occurring in each capacitor of the array as the first step upon power-up and eliminates the need for an extra calibration DAC. Self-trimming is performed digitally during normal ADC operation. The algorithm is implemented on a 14-bit high-voltage input range SAR ADC with integrated dynamic error correction capacitors. The IC is fabricated in 0.6-um high voltage compliant CMOS process, accepting up to 24Vpp differential input signal. The proposed approach achieves 73.32 dB Signal to Noise and Distortion Ratio (SNDR) which is an improvement of 12.03 dB after self-calibration at 400 kS/s sampling rate, consuming 90-mW from a +/-15V supply. The calibration circuitry occupies 28% of the capacitor DAC, and consumes less than 15mW during operation. Measurement results shows that this algorithm reduces INL from as high as 7 LSBs down to 1 LSB and it works even in the presence of larger mismatches exceeding 260 LSBs. Similarly, it reduces DNL errors from 10 LSBs down to 1 LSB. The ADC occupies an active area of 9.76 mm2.
Self Calibration Techniques For Successive Approximation Analog To Digital Converters
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Author : Hae-Seung Lee
language : en
Publisher:
Release Date : 1984
Self Calibration Techniques For Successive Approximation Analog To Digital Converters written by Hae-Seung Lee and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 1984 with categories.
Applying The Split Adc Architecture To A 16 Bit 1 Ms S Differential Successive Approximation Analog To Digital Converter
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Author :
language : en
Publisher:
Release Date : 2008
Applying The Split Adc Architecture To A 16 Bit 1 Ms S Differential Successive Approximation Analog To Digital Converter written by and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2008 with Analog-to-digital converters categories.
Abstract: Successive Approximation (SAR) analog-to-digital converters are used extensively in biomedical applications such as CAT scan due to the high resolution they offer. Capacitor mismatch in the SAR converter is a limiting factor for its accuracy and resolution. Without some form of calibration, a SAR converter can only achieve 10 bit accuracy. In industry, the CAL-DAC approach is a popular approach for calibrating the SAR ADC, but this approach requires significant test time. This thesis applies the "Split-ADC" architecture with a deterministic, digital, and background self-calibration algorithm to the SAR converter to minimize test time. In this approach, a single ADC is split into two independent halves. The two split ADCs convert the same input sample and produce two output codes. The ADC output is the average of these two output codes. The difference between these two codes is used as a calibration signal to estimate the errors of the calibration parameters in a modified Jacobi method. The estimates are used to update calibration parameters are updated in a negative feedback LMS procedure. The ADC is fully calibrated when the difference signal goes to zero on average. This thesis focuses on the specific implementation of the "Split-ADC" self-calibrating algorithm on a 16 bit, 1 MS/s differential SAR ADC. The ADC can be calibrated with 105 conversions. This represents an improvement of 3 orders of magnitude over existing statistically-based calibration algorithms. Simulation results show that the linearity of the calibrated ADC improves to within "1 LSB.
All Digital Calibration For High Resolution Successive Approximation Register Analog To Digital Converter
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Author : 廖亦勛
language : en
Publisher:
Release Date : 2022
All Digital Calibration For High Resolution Successive Approximation Register Analog To Digital Converter written by 廖亦勛 and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2022 with categories.
A Full Range Digital Calibration In 12 Bit Successive Approximation Register Analog To Digital Converter
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Author : 林葦婷
language : en
Publisher:
Release Date : 2013
A Full Range Digital Calibration In 12 Bit Successive Approximation Register Analog To Digital Converter written by 林葦婷 and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2013 with categories.
Advanced Analog To Digital And Digital To Analog Convertors
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Author : Hae-Seung (Harry) Lee
language : en
Publisher: Springer
Release Date : 2010-12-15
Advanced Analog To Digital And Digital To Analog Convertors written by Hae-Seung (Harry) Lee and has been published by Springer this book supported file pdf, txt, epub, kindle and other format this book has been release on 2010-12-15 with Technology & Engineering categories.
This book offers innovative techniques from a research group that has shaped the evolution of analog-to-digital converter design for two decades. It reviews creative approaches across a number of technologies. Coverage includes popular architectures such as pipeline, delta-sigma, successive-approximation, flash and algorithmic converters. The book explores architectural techniques for reducing power consumption and improving linearity and signal-to-noise ratio. These include self-calibration, commutative feedback and mismatch-shaping techniques.
A 12 Bit 10 Ms S Calibration Free Successive Approximation Analog To Digital Converter
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Author : 張力仁
language : en
Publisher:
Release Date : 2019
A 12 Bit 10 Ms S Calibration Free Successive Approximation Analog To Digital Converter written by 張力仁 and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2019 with categories.
Low Power Successive Approximation Analog To Digital Converter With Digital Calibration
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Author : Wei Li
language : en
Publisher:
Release Date : 2014
Low Power Successive Approximation Analog To Digital Converter With Digital Calibration written by Wei Li and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2014 with Successive approximation analog-to-digital converters categories.
IC designers are continuously facing the challenges from reduced CMOS feature sizes and supply voltages. ADCs that deliver satisfactory resolutions/speeds while utilizing the state-of-the-art technologies to save power are in high demand. The analog circuits are more and more assisted by various digital calibration techniques to get boosted performances. This dissertation is focused on a low-power 12-bit 12.5-MS/s successive approximation (SAR) ADC with a couple of calibration schemes. The performances of the proposed SAR ADC are enhanced in two directions. To reduce the power dissipation, a power saving strategy has been proposed. Also, several foreground calibration methods for SAR ADCs have been proposed to reduce power dissipation and enhance conversion accuracy. The design was fabricated in 40nm CMOS technology. Measurement results after calibration showed a SFDR of 82.2 dB, and a THD improvement of 22.5 dB. Finally, two new schemes to realize teraohm on-chip resistance are presented. One of the schemes utilizes a switched-capacitor array, and the other utilizes a switch-capacitor ladder. Using these schemes, large resistances can be fabricated with standard CMOS process in an affordable chip area.
A 16 Bit 500ksps Low Power Successive Approximation Analog To Digital Converter
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Author : Kun Yang
language : en
Publisher:
Release Date : 2009
A 16 Bit 500ksps Low Power Successive Approximation Analog To Digital Converter written by Kun Yang and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2009 with Analog-to-digital converters categories.
A Study Of Capacitor Array Calibration For A Successive Approximation Analog To Digital Converter
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Author : Ji Ma
language : en
Publisher:
Release Date : 2013
A Study Of Capacitor Array Calibration For A Successive Approximation Analog To Digital Converter written by Ji Ma and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2013 with categories.
Analog-to-digital converters (ADCs) are driven by rapid development of mobile communication systems to have higher speed, higher resolution and lower power consumption. Among multiple ADC architectures, successive approximation (SAR) ADCs attract great attention in mixed-signal design community recently. It is due to the fact that they do not contain amplification components and the digital logics are scaling friendly. Therefore, it is easier to design a SAR ADC with smaller component size in advanced technology than other ADC architectures, which decreases the power consumption and increases the speed of the circuit. However, capacitor mismatch limits the minimum size of unit capacitors which could be used for a SAR ADC with more than 10 bit resolution. Large capacitor both limits conversion speed and increases switching power. In this design project, a novel switching scheme and a novel calibration method are adopted to overcome the capacitor mismatch constraint. The switching scheme uses monotonic switching in a SAR ADC to gain one extra bit, and switches a dummy capacitor between the common mode voltage level (Vcm) and the ground (gnd) to obtain another extra bit. To keep the resolution constant, the capacitor number is reduced by two. The calibration method extracts missing code width to estimate the actual value of capacitors. The missing code extraction is accomplished by detecting metastable state of a comparator, forcing the current bit value and using less significant bits to measure the actual capacitor value. Dither method is adopted to improve calibration accuracy. Behavior model simulation is provided to verify the effectiveness of the calibration method. A circuit design of a 12 bit ADC and the simulation for schematic design is presented in this report.