A Full Range Digital Calibration In 12 Bit Successive Approximation Register Analog To Digital Converter
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A Full Range Digital Calibration In 12 Bit Successive Approximation Register Analog To Digital Converter
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Author : 林葦婷
language : en
Publisher:
Release Date : 2013
A Full Range Digital Calibration In 12 Bit Successive Approximation Register Analog To Digital Converter written by 林葦婷 and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2013 with categories.
Statistical Calibration For Two Step Analog To Digital Conversion
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Author : Yi-Long Yu
language : en
Publisher:
Release Date : 2019
Statistical Calibration For Two Step Analog To Digital Conversion written by Yi-Long Yu and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2019 with categories.
This thesis describes a two-step, hybrid and reconfigurable data converter using statistical calibration. The two-step analog-to-digital converter (ADC) has a front-end successive-approximation register (SAR) ADC and a back-end time-domain (TD) ADC, which together form a hybrid converter. An inter-stage sample-and-hold amplifier (SHA) doubles the operating speed by allowing the operation to be pipelined. A reconfigurable characteristic allows the converter resolution to be adjusted to be 8, 10 or 12 bits. Digital statistical calibration of ADCs can be implemented without any changes to the analog circuits, which allows it to be compatible with the characteristics of scaled CMOS, allowing potential savings in area and power dissipation. Unfortunately, statistical calibration requires some assumptions about the input density. However, these assumptions are less restrictive in this work than in previous work for two reasons. First, statistical calibration of the mismatch in the front-end capacitor arrays requires only that the input distribution be smooth (instead of requiring that the input be known as in previous work). Also, statistical calibration of inter-stage and back-end errors relies on the assumption that the residue or quantization error from the first stage is uniformly distributed. This residue characteristic holds for many ADC inputs and is intuitively explained in this thesis. To demonstrate the statistical calibration, a prototype ADC is fabricated in 40-nm CMOS technology. In the 12-bit mode at 20 MS/s, the maximum SNDR is 59 dB before calibration and 68 dB after calibration, using 6.2 fJ per conversion-step, excluding the power dissipation required by the calibration and 9.1 fJ per conversion-step including the estimated power dissipation for the calibration.
A Calibration Service For Analog To Digital And Digital To Analog Converters
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Author : T. Michael Souders
language : en
Publisher:
Release Date : 1981
A Calibration Service For Analog To Digital And Digital To Analog Converters written by T. Michael Souders and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 1981 with Analog-to-digital converters categories.
All Digital Calibration For High Resolution Successive Approximation Register Analog To Digital Converter
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Author : 廖亦勛
language : en
Publisher:
Release Date : 2022
All Digital Calibration For High Resolution Successive Approximation Register Analog To Digital Converter written by 廖亦勛 and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2022 with categories.
A Study Of Capacitor Array Calibration For A Successive Approximation Analog To Digital Converter
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Author : Ji Ma
language : en
Publisher:
Release Date : 2013
A Study Of Capacitor Array Calibration For A Successive Approximation Analog To Digital Converter written by Ji Ma and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2013 with categories.
Analog-to-digital converters (ADCs) are driven by rapid development of mobile communication systems to have higher speed, higher resolution and lower power consumption. Among multiple ADC architectures, successive approximation (SAR) ADCs attract great attention in mixed-signal design community recently. It is due to the fact that they do not contain amplification components and the digital logics are scaling friendly. Therefore, it is easier to design a SAR ADC with smaller component size in advanced technology than other ADC architectures, which decreases the power consumption and increases the speed of the circuit. However, capacitor mismatch limits the minimum size of unit capacitors which could be used for a SAR ADC with more than 10 bit resolution. Large capacitor both limits conversion speed and increases switching power. In this design project, a novel switching scheme and a novel calibration method are adopted to overcome the capacitor mismatch constraint. The switching scheme uses monotonic switching in a SAR ADC to gain one extra bit, and switches a dummy capacitor between the common mode voltage level (Vcm) and the ground (gnd) to obtain another extra bit. To keep the resolution constant, the capacitor number is reduced by two. The calibration method extracts missing code width to estimate the actual value of capacitors. The missing code extraction is accomplished by detecting metastable state of a comparator, forcing the current bit value and using less significant bits to measure the actual capacitor value. Dither method is adopted to improve calibration accuracy. Behavior model simulation is provided to verify the effectiveness of the calibration method. A circuit design of a 12 bit ADC and the simulation for schematic design is presented in this report.
All Digital Background Calibration For Time Interleaved And Successive Approximation Register Analog To Digital Converters
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Author : Christopher Leonidas David
language : en
Publisher:
Release Date : 2010
All Digital Background Calibration For Time Interleaved And Successive Approximation Register Analog To Digital Converters written by Christopher Leonidas David and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2010 with categories.
Abstract: The growth of digital systems underscores the need to convert analog information to the digital domain at high speeds and with great accuracy. Analog-to-Digital Converter (ADC) calibration is often a limiting factor, requiring longer calibration times to achieve higher accuracy. The goal of this dissertation is to perform a fully digital background calibration using an arbitrary input signal for A/D converters. The work presented here adapts the cyclic "Split-ADC" calibration method to the time interleaved (TI) and successive approximation register (SAR) architectures. The TI architecture has three types of linear mismatch errors: offset, gain and aperture time delay. By correcting all three mismatch errors in the digital domain, each converter is capable of operating at the fastest speed allowed by the process technology. The total number of correction parameters required for calibration is dependent on the interleaving ratio, M. To adapt the "Split-ADC" method to a TI system, 2M+1 half-sized converters are required to estimate 3(2M+1) correction parameters. This thesis presents a 4:1 "Split-TI" converter that achieves full convergence in less than 400,000 samples. The SAR architecture employs a binary weight capacitor array to convert analog inputs into digital output codes. Mismatch in the capacitor weights results in non-linear distortion error. By adding redundant bits and dividing the array into individual unit capacitors, the "Split-SAR" method can estimate the mismatch and correct the digital output code. The results from this work show a reduction in the non-linear distortion with the ability to converge in less than 750,000 samples.
Self Calibration And Digital Trimming Of Successive Approximation Analog To Digital Converters
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Author : Shankar Thirunakkarasu
language : en
Publisher:
Release Date : 2014
Self Calibration And Digital Trimming Of Successive Approximation Analog To Digital Converters written by Shankar Thirunakkarasu and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2014 with Successive approximation analog-to-digital converters categories.
Several state of the art, monitoring and control systems, such as DC motorcontrollers, power line monitoring and protection systems, instrumentation systems and battery monitors require direct digitization of a high voltage input signals. Analog-to-Digital Converters (ADCs) that can digitize high voltage signals require high linearity and low voltage coefficient capacitors. A built in self-calibration and digital-trim algorithm correcting static mismatches in Capacitive Digital-to-Analog Converter (CDAC) used in Successive Approximation Register Analog to Digital Converters (SARADCs) is proposed. The algorithm uses a dynamic error correction (DEC) capacitor to cancel the static errors occurring in each capacitor of the array as the first step upon power-up and eliminates the need for an extra calibration DAC. Self-trimming is performed digitally during normal ADC operation. The algorithm is implemented on a 14-bit high-voltage input range SAR ADC with integrated dynamic error correction capacitors. The IC is fabricated in 0.6-um high voltage compliant CMOS process, accepting up to 24Vpp differential input signal. The proposed approach achieves 73.32 dB Signal to Noise and Distortion Ratio (SNDR) which is an improvement of 12.03 dB after self-calibration at 400 kS/s sampling rate, consuming 90-mW from a +/-15V supply. The calibration circuitry occupies 28% of the capacitor DAC, and consumes less than 15mW during operation. Measurement results shows that this algorithm reduces INL from as high as 7 LSBs down to 1 LSB and it works even in the presence of larger mismatches exceeding 260 LSBs. Similarly, it reduces DNL errors from 10 LSBs down to 1 LSB. The ADC occupies an active area of 9.76 mm2.
Circuit Design For Realization Of A 16 Bit 1ms S Successive Approximation Register Analog To Digital Converter
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Author : Cody R. Brenneman
language : en
Publisher:
Release Date : 2010
Circuit Design For Realization Of A 16 Bit 1ms S Successive Approximation Register Analog To Digital Converter written by Cody R. Brenneman and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2010 with categories.
Abstract: As the use of digital systems continues to grow, there is an increasing need to convert analog information into the digital domain. Successive Approximation Register (SAR) analog-to-digital converters are used extensively in this regard due to their high resolution, small die area, and moderate conversion speeds. However, capacitor mismatch within the SAR converter is a limiting factor in its accuracy and resolution. Without some form of calibration, a SAR converter can only reasonably achieve an accuracy of 10 bits. The Split-ADC technique is a digital, deterministic, background self-calibration algorithm that can be applied to the SAR converter. This thesis describes the circuit design and physical implementation of a novel 16-bit 1MS/s SAR analog-to-digital converter for use with the Split-ADC calibration algorithm. The system was designed using the Jazz 0.18um CMOS process, successfully operates at 1MS/s, and consumes a die area of 1.2mm2. The calibration algorithm was applied, showing an improvement in the overall accuracy of the converter.
On Neutrosophic Extended Triplet La Hypergroups And Strong Pure La Semihypergroups
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Author : Minghao Hu
language : en
Publisher: Infinite Study
Release Date :
On Neutrosophic Extended Triplet La Hypergroups And Strong Pure La Semihypergroups written by Minghao Hu and has been published by Infinite Study this book supported file pdf, txt, epub, kindle and other format this book has been release on with Mathematics categories.
We introduce the notions of neutrosophic extended triplet LA-semihypergroup, neutrosophic extended triplet LA-hypergroup, which can reflect some symmetry of hyperoperation and discuss the relationships among them and regular LA-semihypergroups, LA-hypergroups, regular LA-hypergroups. In particular, we introduce the notion of strong pure neutrosophic extended triplet LA-semihypergroup, get some special properties of it and prove the construction theorem about it under the condition of asymmetry. The examples in this paper are all from Python programs.
Applying The Split Adc Architecture To A 16 Bit 1 Ms S Differential Successive Approximation Analog To Digital Converter
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Author :
language : en
Publisher:
Release Date : 2008
Applying The Split Adc Architecture To A 16 Bit 1 Ms S Differential Successive Approximation Analog To Digital Converter written by and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2008 with Analog-to-digital converters categories.
Abstract: Successive Approximation (SAR) analog-to-digital converters are used extensively in biomedical applications such as CAT scan due to the high resolution they offer. Capacitor mismatch in the SAR converter is a limiting factor for its accuracy and resolution. Without some form of calibration, a SAR converter can only achieve 10 bit accuracy. In industry, the CAL-DAC approach is a popular approach for calibrating the SAR ADC, but this approach requires significant test time. This thesis applies the "Split-ADC" architecture with a deterministic, digital, and background self-calibration algorithm to the SAR converter to minimize test time. In this approach, a single ADC is split into two independent halves. The two split ADCs convert the same input sample and produce two output codes. The ADC output is the average of these two output codes. The difference between these two codes is used as a calibration signal to estimate the errors of the calibration parameters in a modified Jacobi method. The estimates are used to update calibration parameters are updated in a negative feedback LMS procedure. The ADC is fully calibrated when the difference signal goes to zero on average. This thesis focuses on the specific implementation of the "Split-ADC" self-calibrating algorithm on a 16 bit, 1 MS/s differential SAR ADC. The ADC can be calibrated with 105 conversions. This represents an improvement of 3 orders of magnitude over existing statistically-based calibration algorithms. Simulation results show that the linearity of the calibrated ADC improves to within "1 LSB.