All Digital Background Calibration For Time Interleaved And Successive Approximation Register Analog To Digital Converters
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All Digital Background Calibration For Time Interleaved And Successive Approximation Register Analog To Digital Converters
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Author : Christopher Leonidas David
language : en
Publisher:
Release Date : 2010
All Digital Background Calibration For Time Interleaved And Successive Approximation Register Analog To Digital Converters written by Christopher Leonidas David and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2010 with categories.
Abstract: The growth of digital systems underscores the need to convert analog information to the digital domain at high speeds and with great accuracy. Analog-to-Digital Converter (ADC) calibration is often a limiting factor, requiring longer calibration times to achieve higher accuracy. The goal of this dissertation is to perform a fully digital background calibration using an arbitrary input signal for A/D converters. The work presented here adapts the cyclic "Split-ADC" calibration method to the time interleaved (TI) and successive approximation register (SAR) architectures. The TI architecture has three types of linear mismatch errors: offset, gain and aperture time delay. By correcting all three mismatch errors in the digital domain, each converter is capable of operating at the fastest speed allowed by the process technology. The total number of correction parameters required for calibration is dependent on the interleaving ratio, M. To adapt the "Split-ADC" method to a TI system, 2M+1 half-sized converters are required to estimate 3(2M+1) correction parameters. This thesis presents a 4:1 "Split-TI" converter that achieves full convergence in less than 400,000 samples. The SAR architecture employs a binary weight capacitor array to convert analog inputs into digital output codes. Mismatch in the capacitor weights results in non-linear distortion error. By adding redundant bits and dividing the array into individual unit capacitors, the "Split-SAR" method can estimate the mismatch and correct the digital output code. The results from this work show a reduction in the non-linear distortion with the ability to converge in less than 750,000 samples.
An Equalization Based Adaptive Digital Background Calibration Technique For Successive Approximation Analog To Digital Converter And Time Interleaved Converter Array
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Author : Wenbo Liu
language : en
Publisher:
Release Date : 2008
An Equalization Based Adaptive Digital Background Calibration Technique For Successive Approximation Analog To Digital Converter And Time Interleaved Converter Array written by Wenbo Liu and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2008 with categories.
Digital Background Calibration Of Analog To Digital Converters Using A Calibration Queue
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Author : Ozan Ersan Erdoğan
language : en
Publisher:
Release Date : 1999
Digital Background Calibration Of Analog To Digital Converters Using A Calibration Queue written by Ozan Ersan Erdoğan and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 1999 with categories.
Calibration Techniques For Time Interleaved Sar A D Converters
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Author : Dusan Vlastimir Stepanovic
language : en
Publisher:
Release Date : 2012
Calibration Techniques For Time Interleaved Sar A D Converters written by Dusan Vlastimir Stepanovic and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2012 with categories.
Benefits of technology scaling and the flexibility of digital circuits favor the digital signal processing in many applications, placing additional burden to the analog-to-digital con- verters (ADCs). This has created a need for energy-efficient ADCs in the GHz sampling frequency and moderate effective resolution range. A dominantly digital nature of successive approximation register (SAR) ADCs makes them a good candidate for an energy-efficient and scalable design, but its sequential operation limits its applicability in the GHz sampling range. Time-interleaving can be used to extend the efficiency of the SAR ADCs to the higher frequencies if the mismatches between the interleaved ADC channels can be handled in an efficient manner. New calibration techniques are proposed for time-interleaved SAR ADCs capable of cor- recting the gain, offset and timing mismatches, as well as the static nonlinearities of individ- ual ADC channels stemming from the capacitor mismatches. The techniques are based on introducing two additional calibration channels that are identical to all other time-interleaved channels and the use of the least mean square algorithm (LMS). The calibration of the chan- nel offset and gain mismatches, as well as the capacitor mismatches, is performed in the background using digital post-processing. The timing mismatches between channels are cor- rected using a mixed-signal feedback, where all calculations are performed in the digital do- main, but the actual timing correction is done in the analog domain by fine-tuning the edges of the sampling clocks. These calibration techniques enable a design of time-interleaved con- verters that use minimum-sized capacitors and operate in the thermal-noise-limited regime for maximum energy and area efficiency. The techniques are demonstrated on a time-interleaved converter that interleaves 24 channels designed in a 65nm CMOS technology. The ADC uses the smallest capacitor value of only 50aF, achieves 50.9dB SNDR at fs = 2.8GHz with the effective-resolution bandwidth higher than the Nyquist frequency, while consuming only 44.6 mW of power.
Time Interleaved Sar Adc With Signal Independent Background Timing Calibration
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Author : Christopher Kaiti Su
language : en
Publisher:
Release Date : 2020
Time Interleaved Sar Adc With Signal Independent Background Timing Calibration written by Christopher Kaiti Su and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2020 with categories.
This thesis describes a background-calibration technique that overcomes timing errors in time-interleaved analog-to-digital converters (ADCs) in a way that is almost independent of the user-provided ADC input signal. Additive dither is widely used to achieve signal-independent background calibration of many errors in data converters [1]. For example, this technique has been used to calibrate for gain mismatch in time-interleaved ADCs [2]. In most cases, however, binary dither has been used, and binary dither is not able to detect timing errors when the user-provided ADC input is zero or constant because timing errors do not produce amplitude errors when the ADC input is constant. This thesis presents a study of the use of a random ramp-based dither signal to calibrate for timing errors in time-interleaved ADCs. To demonstrate the dither-based timing calibration, a prototype 10-bit 500-MS/s 4-channel ADC was fabricated in 40-nm CMOS. With the proposed timing calibration, the Signal-to-Noise-and-Distortion Ratio (SNDR) is 50.1 dB with a user-provided input at 249 MHz while consuming 6.2 mW, giving a figure of merit (FoM) of 48.4 fJ/step. Disabling the ramp after the timing calibration converges improves the SNDR to 51 dB and reduces the power dissipation to 5.8 mW as well as the FoM to 39.8 fJ/step. [1] H. E. Hilton, "A 10-MHz Analog-to-Digital Converter with 110-dB Linearity," Hewlett-Packard Journal, vol. 44, No. 5, pp. 105-112, Oct. 1993. [2] D. Fu, K. C. Dyer, P. J. Hurst, and S. H. Lewis, "A Digital Background Calibration Technique for Time-Interleaved Analog-to-Digital Converters," IEEE J. of Solid-State Circuits, vol. 33, No. 12, pp.1904-1911, Dec. 1998.
All Digital Calibration For High Resolution Successive Approximation Register Analog To Digital Converter
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Author : 廖亦勛
language : en
Publisher:
Release Date : 2022
All Digital Calibration For High Resolution Successive Approximation Register Analog To Digital Converter written by 廖亦勛 and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2022 with categories.
Background Calibration Of Timing Skew In Time Interleaved A D Converters
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Author : Manar Ibrahim El-Chammas
language : en
Publisher: Stanford University
Release Date : 2010
Background Calibration Of Timing Skew In Time Interleaved A D Converters written by Manar Ibrahim El-Chammas and has been published by Stanford University this book supported file pdf, txt, epub, kindle and other format this book has been release on 2010 with categories.
The increasing data rate of wireline communication systems leads to more inter-symbol interference, due to the dispersive properties of the communication channel. This requires more complex equalization blocks to meet the required bit-error rate. One solution is to use an Analog-to-Digital Converter (ADC) in the front-end, thus enabling a digitally-equalized serial link. To achieve the high-data rates of these communication systems, a time-interleaved ADC is typically used. However, this type of ADC suffers from several time-varying errors, the most prominent of which is timing skew. This thesis introduces a statistics-based background calibration algorithm that compensates for the effect of timing skew. To demonstrate the background calibration algorithm, a proof-of-concept 5 bit 12 GS/s flash ADC has been fabricated in a 65 nm CMOS process. The design of this ADC takes into consideration the tight power bounds imposed on serial links by optimizing both the time-interleaved and the sub-ADC architecture. Power consumption is further reduced by using calibration circuits to correct the offset of the flash ADC's comparators. In the measured results, the timing skew correction improves the dynamic performance of the time-interleaved ADC by 12 dB, and the proof-of-concept ADC has the lowest published power consumption for ADCs with sample rates higher than 10 GS/s.
A Full Range Digital Calibration In 12 Bit Successive Approximation Register Analog To Digital Converter
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Author : 林葦婷
language : en
Publisher:
Release Date : 2013
A Full Range Digital Calibration In 12 Bit Successive Approximation Register Analog To Digital Converter written by 林葦婷 and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2013 with categories.
Background Digital Calibration Of Sar Adc With Fast Fpga Emulation
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Author : Guanhua Wang
language : en
Publisher:
Release Date : 2013
Background Digital Calibration Of Sar Adc With Fast Fpga Emulation written by Guanhua Wang and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2013 with Analog-to-digital converters categories.
This dissertation presents a background calibration technique of successive approximation register (SAR) analog-to-digital converter (ADC) and a FPGA emulation platform for fast verification. The bit-weight calibration of a sub-binary weighted SAR ADC is based on the internal redundancy dithering (IRD) technique. A coarse ADC is employed as the reference path to remove the input interference problem in correlation-based background calibration. A custom FPGA emulation platform is developed to verify the proposed calibration approach, which achieves a 3000 speedup for the same simulation executed on a general-purpose microprocessor. Emulation results show that the signal-to-noise plus distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are improved from 56dB to 89dB and 64dB to 115dB, respectively, for a sub-binary-weighted 16-bit SAR ADC with 1% DAC mismatch errors.
Applying The Split Adc Architecture To A 16 Bit 1 Ms S Differential Successive Approximation Analog To Digital Converter
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Author :
language : en
Publisher:
Release Date : 2008
Applying The Split Adc Architecture To A 16 Bit 1 Ms S Differential Successive Approximation Analog To Digital Converter written by and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2008 with Analog-to-digital converters categories.
Abstract: Successive Approximation (SAR) analog-to-digital converters are used extensively in biomedical applications such as CAT scan due to the high resolution they offer. Capacitor mismatch in the SAR converter is a limiting factor for its accuracy and resolution. Without some form of calibration, a SAR converter can only achieve 10 bit accuracy. In industry, the CAL-DAC approach is a popular approach for calibrating the SAR ADC, but this approach requires significant test time. This thesis applies the "Split-ADC" architecture with a deterministic, digital, and background self-calibration algorithm to the SAR converter to minimize test time. In this approach, a single ADC is split into two independent halves. The two split ADCs convert the same input sample and produce two output codes. The ADC output is the average of these two output codes. The difference between these two codes is used as a calibration signal to estimate the errors of the calibration parameters in a modified Jacobi method. The estimates are used to update calibration parameters are updated in a negative feedback LMS procedure. The ADC is fully calibrated when the difference signal goes to zero on average. This thesis focuses on the specific implementation of the "Split-ADC" self-calibrating algorithm on a 16 bit, 1 MS/s differential SAR ADC. The ADC can be calibrated with 105 conversions. This represents an improvement of 3 orders of magnitude over existing statistically-based calibration algorithms. Simulation results show that the linearity of the calibrated ADC improves to within "1 LSB.