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Calibration Techniques For Time Interleaved Sar A D Converters


Calibration Techniques For Time Interleaved Sar A D Converters
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Calibration Techniques For Time Interleaved Sar A D Converters


Calibration Techniques For Time Interleaved Sar A D Converters
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Author : Dusan Vlastimir Stepanovic
language : en
Publisher:
Release Date : 2012

Calibration Techniques For Time Interleaved Sar A D Converters written by Dusan Vlastimir Stepanovic and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2012 with categories.


Benefits of technology scaling and the flexibility of digital circuits favor the digital signal processing in many applications, placing additional burden to the analog-to-digital con- verters (ADCs). This has created a need for energy-efficient ADCs in the GHz sampling frequency and moderate effective resolution range. A dominantly digital nature of successive approximation register (SAR) ADCs makes them a good candidate for an energy-efficient and scalable design, but its sequential operation limits its applicability in the GHz sampling range. Time-interleaving can be used to extend the efficiency of the SAR ADCs to the higher frequencies if the mismatches between the interleaved ADC channels can be handled in an efficient manner. New calibration techniques are proposed for time-interleaved SAR ADCs capable of cor- recting the gain, offset and timing mismatches, as well as the static nonlinearities of individ- ual ADC channels stemming from the capacitor mismatches. The techniques are based on introducing two additional calibration channels that are identical to all other time-interleaved channels and the use of the least mean square algorithm (LMS). The calibration of the chan- nel offset and gain mismatches, as well as the capacitor mismatches, is performed in the background using digital post-processing. The timing mismatches between channels are cor- rected using a mixed-signal feedback, where all calculations are performed in the digital do- main, but the actual timing correction is done in the analog domain by fine-tuning the edges of the sampling clocks. These calibration techniques enable a design of time-interleaved con- verters that use minimum-sized capacitors and operate in the thermal-noise-limited regime for maximum energy and area efficiency. The techniques are demonstrated on a time-interleaved converter that interleaves 24 channels designed in a 65nm CMOS technology. The ADC uses the smallest capacitor value of only 50aF, achieves 50.9dB SNDR at fs = 2.8GHz with the effective-resolution bandwidth higher than the Nyquist frequency, while consuming only 44.6 mW of power.



Time Interleaved Sar Adc With Signal Independent Background Timing Calibration


Time Interleaved Sar Adc With Signal Independent Background Timing Calibration
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Author : Christopher Kaiti Su
language : en
Publisher:
Release Date : 2020

Time Interleaved Sar Adc With Signal Independent Background Timing Calibration written by Christopher Kaiti Su and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2020 with categories.


This thesis describes a background-calibration technique that overcomes timing errors in time-interleaved analog-to-digital converters (ADCs) in a way that is almost independent of the user-provided ADC input signal. Additive dither is widely used to achieve signal-independent background calibration of many errors in data converters [1]. For example, this technique has been used to calibrate for gain mismatch in time-interleaved ADCs [2]. In most cases, however, binary dither has been used, and binary dither is not able to detect timing errors when the user-provided ADC input is zero or constant because timing errors do not produce amplitude errors when the ADC input is constant. This thesis presents a study of the use of a random ramp-based dither signal to calibrate for timing errors in time-interleaved ADCs. To demonstrate the dither-based timing calibration, a prototype 10-bit 500-MS/s 4-channel ADC was fabricated in 40-nm CMOS. With the proposed timing calibration, the Signal-to-Noise-and-Distortion Ratio (SNDR) is 50.1 dB with a user-provided input at 249 MHz while consuming 6.2 mW, giving a figure of merit (FoM) of 48.4 fJ/step. Disabling the ramp after the timing calibration converges improves the SNDR to 51 dB and reduces the power dissipation to 5.8 mW as well as the FoM to 39.8 fJ/step. [1] H. E. Hilton, "A 10-MHz Analog-to-Digital Converter with 110-dB Linearity," Hewlett-Packard Journal, vol. 44, No. 5, pp. 105-112, Oct. 1993. [2] D. Fu, K. C. Dyer, P. J. Hurst, and S. H. Lewis, "A Digital Background Calibration Technique for Time-Interleaved Analog-to-Digital Converters," IEEE J. of Solid-State Circuits, vol. 33, No. 12, pp.1904-1911, Dec. 1998.



Calibration Techniques For High Speed Time Interleaved Sar Adc


Calibration Techniques For High Speed Time Interleaved Sar Adc
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Author : Benwei Xu
language : en
Publisher:
Release Date : 2017

Calibration Techniques For High Speed Time Interleaved Sar Adc written by Benwei Xu and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2017 with Multiplexing categories.


The emerging applications such as Internet-of-Things (IoT), self-driven car and artificial intelligence (AI) trigger rapid increase in bandwidth demand in data centers and telecommunication infrastructure. The data traffic in global network is expected to be tripled by 2020 and the ITRS predicts the IO speed to exceed 60GB/s in 2020. ADC-based backplane receivers and coherent fiber-optical receivers are promising technologies for the next generation wireline communication systems. For both technologies, high speed analog-to-digital converter (ADC) of over 20GS/s is one key enabler. For 5G wireless communication system high resolution ADC (12bit) with sampling speed over 1GHz is required. Many other application also demands ADC with performance that has never been achieved before while only provides a strict power budget. Time-interleaving massive slow-but-efficient subADCs to achieve the target is one practical way. However, the benefit brought by time-interleaving is not free. Mismatch between subADCs often limits its linearity making the performance of the array far from the individual subADCs. Among all different kinds of mismatches, dynamic mismatch including skew and bandwidth mismatch are the hardest to identify and cure. This dissertation will introduce two different methods to calibrate the skew mismatch of TI-ADC. Two fabricated chip 12b 1GS/s and 6b 24GS/s will be shown as the silicon verification of the proposed methods.



High Resolution And High Speed Integrated Cmos Ad Converters For Low Power Applications


High Resolution And High Speed Integrated Cmos Ad Converters For Low Power Applications
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Author : Weitao Li
language : en
Publisher: Springer
Release Date : 2017-08-01

High Resolution And High Speed Integrated Cmos Ad Converters For Low Power Applications written by Weitao Li and has been published by Springer this book supported file pdf, txt, epub, kindle and other format this book has been release on 2017-08-01 with Technology & Engineering categories.


This book is a step-by-step tutorial on how to design a low-power, high-resolution (not less than 12 bit), and high-speed (not less than 200 MSps) integrated CMOS analog-to-digital (AD) converter, to respond to the challenge from the rapid growth of IoT. The discussion includes design techniques on both the system level and the circuit block level. In the architecture level, the power-efficient pipelined AD converter, the hybrid AD converter and the time-interleaved AD converter are described. In the circuit block level, the reference voltage buffer, the opamp, the comparator, and the calibration are presented. Readers designing low-power and high-performance AD converters won’t want to miss this invaluable reference. Provides an in-depth introduction to the newest design techniques for the power-efficient, high-resolution (not less than 12 bit), and high-speed (not less than 200 MSps) AD converter; Presents three types of power-efficient architectures of the high-resolution and high-speed AD converter; Discusses the relevant circuit blocks (i.e., the reference voltage buffer, the opamp, and the comparator) in two aspects, relaxing the requirements and improving the performance.



All Digital Background Calibration For Time Interleaved And Successive Approximation Register Analog To Digital Converters


All Digital Background Calibration For Time Interleaved And Successive Approximation Register Analog To Digital Converters
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Author : Christopher Leonidas David
language : en
Publisher:
Release Date : 2010

All Digital Background Calibration For Time Interleaved And Successive Approximation Register Analog To Digital Converters written by Christopher Leonidas David and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2010 with categories.


Abstract: The growth of digital systems underscores the need to convert analog information to the digital domain at high speeds and with great accuracy. Analog-to-Digital Converter (ADC) calibration is often a limiting factor, requiring longer calibration times to achieve higher accuracy. The goal of this dissertation is to perform a fully digital background calibration using an arbitrary input signal for A/D converters. The work presented here adapts the cyclic "Split-ADC" calibration method to the time interleaved (TI) and successive approximation register (SAR) architectures. The TI architecture has three types of linear mismatch errors: offset, gain and aperture time delay. By correcting all three mismatch errors in the digital domain, each converter is capable of operating at the fastest speed allowed by the process technology. The total number of correction parameters required for calibration is dependent on the interleaving ratio, M. To adapt the "Split-ADC" method to a TI system, 2M+1 half-sized converters are required to estimate 3(2M+1) correction parameters. This thesis presents a 4:1 "Split-TI" converter that achieves full convergence in less than 400,000 samples. The SAR architecture employs a binary weight capacitor array to convert analog inputs into digital output codes. Mismatch in the capacitor weights results in non-linear distortion error. By adding redundant bits and dividing the array into individual unit capacitors, the "Split-SAR" method can estimate the mismatch and correct the digital output code. The results from this work show a reduction in the non-linear distortion with the ability to converge in less than 750,000 samples.



Calibration Techniques In Nyquist A D Converters


Calibration Techniques In Nyquist A D Converters
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Author : Hendrik van der Ploeg
language : en
Publisher: Springer Science & Business Media
Release Date : 2006-09-13

Calibration Techniques In Nyquist A D Converters written by Hendrik van der Ploeg and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2006-09-13 with Technology & Engineering categories.


This book analyses different A/D-converter architectures with an emphasis on the maximum achievable power efficiency. It also provides an accessible overview of the state-of-the art in calibration techniques for Nyquist A/D converters. The calibration techniques presented are applicable to other analog-to-digital systems, such as those applied in integrated receivers. They allow implementation without introducing a speed or power penalty.



Calibration Technique Based On Lstm Regression Neural Network For Time Interleaved Sar Analog To Digital Converter


Calibration Technique Based On Lstm Regression Neural Network For Time Interleaved Sar Analog To Digital Converter
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Author :
language : en
Publisher:
Release Date : 2021

Calibration Technique Based On Lstm Regression Neural Network For Time Interleaved Sar Analog To Digital Converter written by and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2021 with categories.




Timing Skew Calibration For Time Interleaved Analog To Digital Converters


Timing Skew Calibration For Time Interleaved Analog To Digital Converters
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Author : Luke Wang
language : en
Publisher:
Release Date : 2014

Timing Skew Calibration For Time Interleaved Analog To Digital Converters written by Luke Wang and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2014 with categories.




Signal Reconstruction Algorithms For Time Interleaved Adcs


Signal Reconstruction Algorithms For Time Interleaved Adcs
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Author : Anu Kalidas Muralidharan Pillai
language : en
Publisher: Linköping University Electronic Press
Release Date : 2015-05-22

Signal Reconstruction Algorithms For Time Interleaved Adcs written by Anu Kalidas Muralidharan Pillai and has been published by Linköping University Electronic Press this book supported file pdf, txt, epub, kindle and other format this book has been release on 2015-05-22 with Algorithms categories.


An analog-to-digital converter (ADC) is a key component in many electronic systems. It is used to convert analog signals to the equivalent digital form. The conversion involves sampling which is the process of converting a continuous-time signal to a sequence of discrete-time samples, and quantization in which each sampled value is represented using a finite number of bits. The sampling rate and the effective resolution (number of bits) are two key ADC performance metrics. Today, ADCs form a major bottleneck in many applications like communication systems since it is difficult to simultaneously achieve high sampling rate and high resolution. Among the various ADC architectures, the time-interleaved analog-to-digital converter (TI-ADC) has emerged as a popular choice for achieving very high sampling rates and resolutions. At the principle level, by interleaving the outputs of M identical channel ADCs, a TI-ADC could achieve the same resolution as that of a channel ADC but with M times higher bandwidth. However, in practice, mismatches between the channel ADCs result in a nonuniformly sampled signal at the output of a TI-ADC which reduces the achievable resolution. Often, in TIADC implementations, digital reconstructors are used to recover the uniform-grid samples from the nonuniformly sampled signal at the output of the TI-ADC. Since such reconstructors operate at the TI-ADC output rate, reducing the number of computations required per corrected output sample helps to reduce the power consumed by the TI-ADC. Also, as the mismatch parameters change occasionally, the reconstructor should support online reconfiguration with minimal or no redesign. Further, it is advantageous to have reconstruction schemes that require fewer coefficient updates during reconfiguration. In this thesis, we focus on reducing the design and implementation complexities of nonrecursive finite-length impulse response (FIR) reconstructors. We propose efficient reconstruction schemes for three classes of nonuniformly sampled signals that can occur at the output of TI-ADCs. Firstly, we consider a class of nonuniformly sampled signals that occur as a result of static timing mismatch errors or due to channel mismatches in TI-ADCs. For this type of nonuniformly sampled signals, we propose three reconstructors which utilize a two-rate approach to derive the corresponding single-rate structure. The two-rate based reconstructors move part of the complexity to a symmetric filter and also simplifies the reconstruction problem. The complexity reduction stems from the fact that half of the impulse response coefficients of the symmetric filter are equal to zero and that, compared to the original reconstruction problem, the simplified problem requires only a simpler reconstructor. Next, we consider the class of nonuniformly sampled signals that occur when a TI-ADC is used for sub-Nyquist cyclic nonuniform sampling (CNUS) of sparse multi-band signals. Sub-Nyquist sampling utilizes the sparsities in the analog signal to sample the signal at a lower rate. However, the reduced sampling rate comes at the cost of additional digital signal processing that is needed to reconstruct the uniform-grid sequence from the sub-Nyquist sampled sequence obtained via CNUS. The existing reconstruction scheme is computationally intensive and time consuming and offsets the gains obtained from the reduced sampling rate. Also, in applications where the band locations of the sparse multi-band signal can change from time to time, the reconstructor should support online reconfigurability. Here, we propose a reconstruction scheme that reduces the computational complexity of the reconstructor and at the same time, simplifies the online reconfigurability of the reconstructor. Finally, we consider a class of nonuniformly sampled signals which occur at the output of TI-ADCs that use some of the input sampling instants for sampling a known calibration signal. The samples corresponding to the calibration signal are used for estimating the channel mismatch parameters. In such TI-ADCs, nonuniform sampling is due to the mismatches between the channel ADCs and due to the missing input samples corresponding to the sampling instants reserved for the calibration signal. We propose three reconstruction schemes for such nonuniformly sampled signals and show using design examples that, compared to a previous solution, the proposed schemes require substantially lower computational complexity.



Advanced Data Converters


Advanced Data Converters
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Author : Gabriele Manganaro
language : en
Publisher: Cambridge University Press
Release Date : 2011-11-17

Advanced Data Converters written by Gabriele Manganaro and has been published by Cambridge University Press this book supported file pdf, txt, epub, kindle and other format this book has been release on 2011-11-17 with Technology & Engineering categories.


Need to get up to speed quickly on the latest advances in high performance data converters? Want help choosing the best architecture for your application? With everything you need to know about the key new converter architectures, this guide is for you. It presents basic principles, circuit and system design techniques and associated trade-offs, doing away with lengthy mathematical proofs and providing intuitive descriptions upfront. Everything from time-to-digital converters to comparator-based/zero-crossing ADCs is covered and each topic is introduced with a short summary of the essential basics. Practical examples describing actual chips, along with extensive comparison between architectural or circuit options, ease architecture selection and help you cut design time and engineering risk. Trade-offs, advantages and disadvantages of each option are put into perspective with a discussion of future trends, showing where this field is heading, what is driving it and what the most important unanswered questions are.