Calibration Techniques For High Speed Time Interleaved Sar Adc
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Calibration Techniques For High Speed Time Interleaved Sar Adc
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Author : Benwei Xu
language : en
Publisher:
Release Date : 2017
Calibration Techniques For High Speed Time Interleaved Sar Adc written by Benwei Xu and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2017 with Multiplexing categories.
The emerging applications such as Internet-of-Things (IoT), self-driven car and artificial intelligence (AI) trigger rapid increase in bandwidth demand in data centers and telecommunication infrastructure. The data traffic in global network is expected to be tripled by 2020 and the ITRS predicts the IO speed to exceed 60GB/s in 2020. ADC-based backplane receivers and coherent fiber-optical receivers are promising technologies for the next generation wireline communication systems. For both technologies, high speed analog-to-digital converter (ADC) of over 20GS/s is one key enabler. For 5G wireless communication system high resolution ADC (12bit) with sampling speed over 1GHz is required. Many other application also demands ADC with performance that has never been achieved before while only provides a strict power budget. Time-interleaving massive slow-but-efficient subADCs to achieve the target is one practical way. However, the benefit brought by time-interleaving is not free. Mismatch between subADCs often limits its linearity making the performance of the array far from the individual subADCs. Among all different kinds of mismatches, dynamic mismatch including skew and bandwidth mismatch are the hardest to identify and cure. This dissertation will introduce two different methods to calibrate the skew mismatch of TI-ADC. Two fabricated chip 12b 1GS/s and 6b 24GS/s will be shown as the silicon verification of the proposed methods.
Mismatch Calibration Techniques For Low Power High Speed Time Interleaved Adc
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Author : Ming Qiang Guo
language : en
Publisher:
Release Date : 2019
Mismatch Calibration Techniques For Low Power High Speed Time Interleaved Adc written by Ming Qiang Guo and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2019 with categories.
Calibration Techniques For Time Interleaved Sar A D Converters
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Author : Dusan Vlastimir Stepanovic
language : en
Publisher:
Release Date : 2012
Calibration Techniques For Time Interleaved Sar A D Converters written by Dusan Vlastimir Stepanovic and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2012 with categories.
Benefits of technology scaling and the flexibility of digital circuits favor the digital signal processing in many applications, placing additional burden to the analog-to-digital con- verters (ADCs). This has created a need for energy-efficient ADCs in the GHz sampling frequency and moderate effective resolution range. A dominantly digital nature of successive approximation register (SAR) ADCs makes them a good candidate for an energy-efficient and scalable design, but its sequential operation limits its applicability in the GHz sampling range. Time-interleaving can be used to extend the efficiency of the SAR ADCs to the higher frequencies if the mismatches between the interleaved ADC channels can be handled in an efficient manner. New calibration techniques are proposed for time-interleaved SAR ADCs capable of cor- recting the gain, offset and timing mismatches, as well as the static nonlinearities of individ- ual ADC channels stemming from the capacitor mismatches. The techniques are based on introducing two additional calibration channels that are identical to all other time-interleaved channels and the use of the least mean square algorithm (LMS). The calibration of the chan- nel offset and gain mismatches, as well as the capacitor mismatches, is performed in the background using digital post-processing. The timing mismatches between channels are cor- rected using a mixed-signal feedback, where all calculations are performed in the digital do- main, but the actual timing correction is done in the analog domain by fine-tuning the edges of the sampling clocks. These calibration techniques enable a design of time-interleaved con- verters that use minimum-sized capacitors and operate in the thermal-noise-limited regime for maximum energy and area efficiency. The techniques are demonstrated on a time-interleaved converter that interleaves 24 channels designed in a 65nm CMOS technology. The ADC uses the smallest capacitor value of only 50aF, achieves 50.9dB SNDR at fs = 2.8GHz with the effective-resolution bandwidth higher than the Nyquist frequency, while consuming only 44.6 mW of power.
High Resolution And High Speed Integrated Cmos Ad Converters For Low Power Applications
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Author : Weitao Li
language : en
Publisher: Springer
Release Date : 2017-08-01
High Resolution And High Speed Integrated Cmos Ad Converters For Low Power Applications written by Weitao Li and has been published by Springer this book supported file pdf, txt, epub, kindle and other format this book has been release on 2017-08-01 with Technology & Engineering categories.
This book is a step-by-step tutorial on how to design a low-power, high-resolution (not less than 12 bit), and high-speed (not less than 200 MSps) integrated CMOS analog-to-digital (AD) converter, to respond to the challenge from the rapid growth of IoT. The discussion includes design techniques on both the system level and the circuit block level. In the architecture level, the power-efficient pipelined AD converter, the hybrid AD converter and the time-interleaved AD converter are described. In the circuit block level, the reference voltage buffer, the opamp, the comparator, and the calibration are presented. Readers designing low-power and high-performance AD converters won’t want to miss this invaluable reference. Provides an in-depth introduction to the newest design techniques for the power-efficient, high-resolution (not less than 12 bit), and high-speed (not less than 200 MSps) AD converter; Presents three types of power-efficient architectures of the high-resolution and high-speed AD converter; Discusses the relevant circuit blocks (i.e., the reference voltage buffer, the opamp, and the comparator) in two aspects, relaxing the requirements and improving the performance.
Time Interleaved Sar Adc With Signal Independent Background Timing Calibration
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Author : Christopher Kaiti Su
language : en
Publisher:
Release Date : 2020
Time Interleaved Sar Adc With Signal Independent Background Timing Calibration written by Christopher Kaiti Su and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2020 with categories.
This thesis describes a background-calibration technique that overcomes timing errors in time-interleaved analog-to-digital converters (ADCs) in a way that is almost independent of the user-provided ADC input signal. Additive dither is widely used to achieve signal-independent background calibration of many errors in data converters [1]. For example, this technique has been used to calibrate for gain mismatch in time-interleaved ADCs [2]. In most cases, however, binary dither has been used, and binary dither is not able to detect timing errors when the user-provided ADC input is zero or constant because timing errors do not produce amplitude errors when the ADC input is constant. This thesis presents a study of the use of a random ramp-based dither signal to calibrate for timing errors in time-interleaved ADCs. To demonstrate the dither-based timing calibration, a prototype 10-bit 500-MS/s 4-channel ADC was fabricated in 40-nm CMOS. With the proposed timing calibration, the Signal-to-Noise-and-Distortion Ratio (SNDR) is 50.1 dB with a user-provided input at 249 MHz while consuming 6.2 mW, giving a figure of merit (FoM) of 48.4 fJ/step. Disabling the ramp after the timing calibration converges improves the SNDR to 51 dB and reduces the power dissipation to 5.8 mW as well as the FoM to 39.8 fJ/step. [1] H. E. Hilton, "A 10-MHz Analog-to-Digital Converter with 110-dB Linearity," Hewlett-Packard Journal, vol. 44, No. 5, pp. 105-112, Oct. 1993. [2] D. Fu, K. C. Dyer, P. J. Hurst, and S. H. Lewis, "A Digital Background Calibration Technique for Time-Interleaved Analog-to-Digital Converters," IEEE J. of Solid-State Circuits, vol. 33, No. 12, pp.1904-1911, Dec. 1998.
All Digital Background Calibration For Time Interleaved And Successive Approximation Register Analog To Digital Converters
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Author : Christopher Leonidas David
language : en
Publisher:
Release Date : 2010
All Digital Background Calibration For Time Interleaved And Successive Approximation Register Analog To Digital Converters written by Christopher Leonidas David and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2010 with categories.
Abstract: The growth of digital systems underscores the need to convert analog information to the digital domain at high speeds and with great accuracy. Analog-to-Digital Converter (ADC) calibration is often a limiting factor, requiring longer calibration times to achieve higher accuracy. The goal of this dissertation is to perform a fully digital background calibration using an arbitrary input signal for A/D converters. The work presented here adapts the cyclic "Split-ADC" calibration method to the time interleaved (TI) and successive approximation register (SAR) architectures. The TI architecture has three types of linear mismatch errors: offset, gain and aperture time delay. By correcting all three mismatch errors in the digital domain, each converter is capable of operating at the fastest speed allowed by the process technology. The total number of correction parameters required for calibration is dependent on the interleaving ratio, M. To adapt the "Split-ADC" method to a TI system, 2M+1 half-sized converters are required to estimate 3(2M+1) correction parameters. This thesis presents a 4:1 "Split-TI" converter that achieves full convergence in less than 400,000 samples. The SAR architecture employs a binary weight capacitor array to convert analog inputs into digital output codes. Mismatch in the capacitor weights results in non-linear distortion error. By adding redundant bits and dividing the array into individual unit capacitors, the "Split-SAR" method can estimate the mismatch and correct the digital output code. The results from this work show a reduction in the non-linear distortion with the ability to converge in less than 750,000 samples.
Low Power High Speed Adc Design Techniques In Scaled Cmos Process
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Author : Jeonggoo Song
language : en
Publisher:
Release Date : 2017
Low Power High Speed Adc Design Techniques In Scaled Cmos Process written by Jeonggoo Song and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2017 with categories.
The power consumption of a single-channel successive approximation register (SAR) analog-to-digital (ADC) tends to linearly increase with its sampling rate (f[subscript s]), when f[subscript s] is small. However, when f[subscript s] passes a certain point for a given technology node, the ADC power P increases at much higher rate and the normalized power efficiency (P/f[subscript s]) starts to degrade rapidly. To enhance the conversion speed of SAR ADC, while maintaining a good power efficiency, this thesis presents speed-enhancing techniques for SAR ADC in nano-scale CMOS technologies. First chapter presents a 2b/cycle hybrid SAR architecture with only 1 differential capacitor-DAC (CDAC). Unlike prior multi-bit/cycle SAR works that make use of only the DAC differential mode (DM) voltage, the proposed architecture exploits both the DM and the common mode (CM). By using two degrees of freedom, 2b/cycle conversion technique can boost the f[subscript s] of the ADC without any additional DAC arrays. High-speed ADCs can boost the conversion speed not only by increasing the f[subscript s] of a single-channel ADC, but also by time-interleaving multiple ADC sub-channels running at a lower rate. For an N-channel time-interleaved (TI) SAR ADC operating at f[subscript s], each sub-SAR channel only needs to operate at f[subscript s]=N. Therefore, each sub-SAR can operate in the linear power versus speed region, leading to a significant power saving compared to a single-channel ADC running at the same sampling rate. Despite of its power efficiency, TI-ADC suffers from mismatches among sub-ADC channels, including gain, offset, and timing mismatches. Among them, timing skew is one of the most difficult errors to calibrate as it is nontrivial to extract and its induced error depends on both the frequency and the amplitude of the input signal. Second chapter of this thesis presents a TI-SAR with a fast variance-based timing-skew calibration technique. It uses a single-comparator based window detector (WD) to calibrate the timing skew. The WD suppresses variance estimation errors and allow precise variance estimation from a significantly small number of samples. It has low-hardware cost and orders of magnitude faster convergence speed compared to prior variance-based timing-skew calibration technique. The last chapter presents another TI-SAR with mean absolute deviation (MAD) based timing-skew calibration technique. In addition to all the advantages presented with the fast variance-based timing-skew calibration technique, the proposed technique further reduces the digital computation power by 50% by eliminating the squaring operations, which are essential in variance-based calibration technique
Efficient Track And Hold Techniques For High Speed Time Interleaved Adcs
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Author : Xiao Wang
language : en
Publisher:
Release Date : 2018
Efficient Track And Hold Techniques For High Speed Time Interleaved Adcs written by Xiao Wang and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2018 with categories.
Time-Interleaving (TI) can relax the power-speed tradeoffs of analog-to-digital converter (ADC) and reduce their metastability error rate while it is not free. Track-and-hold (T&H) nonlinearity, noise and power are the main limitations of high-speed high-resolution and low-power ADCs. This dissertation introduces two efficient T&H design techniques to improve the performances of TI-ADCs without sophisticated calibrations. Two fabricated chips with 8b 2GS/s and 8b 8.8GS/s will be shown as the silicon verification of the proposed methods. Two prototype ICs were designed during this work. First, a two-way time-interleaved pipelined ADC architecture was built upon a new concept of virtual-ground sampling, featuring merged front-end T/H, residue generation, input termination, and buffering. This architecture is investigated to alleviate the front-end performance tradeoff among the THD, bandwidth, and sample rate (interleaving factor). A 2-GS/s 8b ADC using the new architecture was designed and fabricated in a 28-nm CMOS, achieving 43-dB SNDR and 55-dB SFDR up to Nyquist frequency. Second, a complementary dual-loop-assisted track-and-hold buffer is introduced to achieve both high linearity and bandwidth with low power. The prototype ADC also employs a two-level 2i 8 master-slave hierarchical interleaved architecture and achieved an 8.8 GS/s 16-way time-interleaved asynchronous SAR ADC fabricated in 28-nm CMOS technology. It achieves 38.4-dB SNDR and 50-dB SFDR with a Nyquist input at 8.8 GS/s sampling rate and consumes 83.4 mW, resulting in a 140 fJ/conv.-step Walden FOM with buffers.
Calibration Of Sampling Clock Skew In High Speed High Resolution Time Interleaved Adcs
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Author : Daniel Prashanth Kumar
language : en
Publisher:
Release Date : 2015
Calibration Of Sampling Clock Skew In High Speed High Resolution Time Interleaved Adcs written by Daniel Prashanth Kumar and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2015 with categories.
There is an ever-increasing demand for high-resolution and high-resolution ADCs. In order to raise the sampling rates of ADCs in a power efficient manner, time-interleaving is an essential technique, whereby N ADC channels, each operating at a sampling frequency of fs, are used to achieve an effective conversion rate of N - fs. While time-interleaving enables higher conversion rates in a given technology, mismatch issues such as gain, offset, and sampling clock skew between channels degrade the overall time-interleaved ADC performance. Of these issues, sampling clock skew between channels is the biggest problem in high-speed and high-resolution, time-interleaved ADCs as errors due to sampling clock skew become more severe for higher input frequencies. There are a few sources of sampling clock skew between channels. Mismatches in the sampling clock path and logic delays are the most obvious ones. Input signal routing mismatch and RC mismatch of the input sampling circuits also cause sampling clock skew. In this thesis, we developed two new methods to mitigate the effects of sampling clock skew in time-interleaved ADCs. The first is the rapid consecutive sampling method, whereby each interleaved channel is implemented using two sub-channel ADCs. Two consecutive samples of the input are taken with a short time delay between them. This allows for a straight-forward linear interpolation between the consecutive samples in order to recover the de-skewed sample. The second method entails introducing a programmable delay in the input signal path, instead of delaying the sampling clock, in order to calibrate out sampling clock skew. The design and implementation of a proof-of-concept, time-interleaved ADC that implements the input signal delay method is detailed. Finally, measurement results to show the efficacy of the proposed method in mitigating the effects of sampling clock skew is also presented.
Time Interleaved Analog To Digital Converters
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Author : Simon Louwsma
language : en
Publisher: Springer Science & Business Media
Release Date : 2010-09-08
Time Interleaved Analog To Digital Converters written by Simon Louwsma and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2010-09-08 with Technology & Engineering categories.
Time-interleaved Analog-to-Digital Converters describes the research performed on low-power time-interleaved ADCs. A detailed theoretical analysis is made of the time-interleaved Track & Hold, since it must be capable of handling signals in the GHz range with little distortion, and minimal power consumption. Timing calibration is not attractive, therefore design techniques are presented which do not require timing calibration. The design of power efficient sub-ADCs is addressed with a theoretical analysis of a successive approximation converter and a pipeline converter. It turns out that the first can consume about 10 times less power than the latter, and this conclusion is supported by literature. Time-interleaved Analog-to-Digital Converters describes the design of a high performance time-interleaved ADC, with much attention for practical design aspects, aiming at both industry and research. Measurements show best-inclass performance with a sample-rate of 1.8 GS/s, 7.9 ENOBs and a power efficiency of 1 pJ/conversion-step.