Efficient Track And Hold Techniques For High Speed Time Interleaved Adcs
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Efficient Track And Hold Techniques For High Speed Time Interleaved Adcs
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Author : Xiao Wang
language : en
Publisher:
Release Date : 2018
Efficient Track And Hold Techniques For High Speed Time Interleaved Adcs written by Xiao Wang and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2018 with categories.
Time-Interleaving (TI) can relax the power-speed tradeoffs of analog-to-digital converter (ADC) and reduce their metastability error rate while it is not free. Track-and-hold (T&H) nonlinearity, noise and power are the main limitations of high-speed high-resolution and low-power ADCs. This dissertation introduces two efficient T&H design techniques to improve the performances of TI-ADCs without sophisticated calibrations. Two fabricated chips with 8b 2GS/s and 8b 8.8GS/s will be shown as the silicon verification of the proposed methods. Two prototype ICs were designed during this work. First, a two-way time-interleaved pipelined ADC architecture was built upon a new concept of virtual-ground sampling, featuring merged front-end T/H, residue generation, input termination, and buffering. This architecture is investigated to alleviate the front-end performance tradeoff among the THD, bandwidth, and sample rate (interleaving factor). A 2-GS/s 8b ADC using the new architecture was designed and fabricated in a 28-nm CMOS, achieving 43-dB SNDR and 55-dB SFDR up to Nyquist frequency. Second, a complementary dual-loop-assisted track-and-hold buffer is introduced to achieve both high linearity and bandwidth with low power. The prototype ADC also employs a two-level 2i 8 master-slave hierarchical interleaved architecture and achieved an 8.8 GS/s 16-way time-interleaved asynchronous SAR ADC fabricated in 28-nm CMOS technology. It achieves 38.4-dB SNDR and 50-dB SFDR with a Nyquist input at 8.8 GS/s sampling rate and consumes 83.4 mW, resulting in a 140 fJ/conv.-step Walden FOM with buffers.
Design Techniques For Ultra High Speed Time Interleaved Analog To Digital Converters
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Author : Yida Duan
language : en
Publisher:
Release Date : 2015
Design Techniques For Ultra High Speed Time Interleaved Analog To Digital Converters written by Yida Duan and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2015 with categories.
Analog-to-Digital Converters (ADCs) serve as the interfaces between the analog natural world and the binary world of computer data. Due to this essential role, ADC circuits have been well studied over 40 years, and many problems associated with them have already been solved. However in recent years, a new species of ADCs has appeared, and since then attracted lots of attention. These are ultra-high-speed (often greater than 40GS/s) time-interleaved ADCs of low or medium resolution (around 6 to 8 bit) built in CMOS processes. Although such ADCs can be used in high-speed electronic measurement equipment and radar systems, the recent driving force behind them is next generation 100Gbps/400Gbps fiber optical transceivers. These transceivers take advantage of ultra-high-speed ADCs and digital-signal-processors (DSPs) to enable ultra-high data-rate communications in long-haul networks (city-to-city, transcontinental, and transoceanic fiber links), metro networks (fibers that connect enterprises in metropolitan areas), and data centers (fiber links within data center infrastructures). At such high sampling rate, massively time-interleaved successive-approximation ADC (SAR ADC) architecture has emerged as the dominant solution due to its excellent power efficiency. Several recent works has demonstrated success in achieving high sampling rate. However, the sampling network has become the bottleneck that limits the input bandwidth in these ADCs. It is apparent that conventional switch-based track-and-hold (T&H) circuit cannot satisfy the >20GHz bandwidth requirement. In addition, it is unclear what the optimal interleaving configuration is. Each state-of-the-art design adopts a different interleaving configuration - from straightforward conventional 1-rank interleaving to 2-rank hierarchical sampling or even 3 ranks. How to partition interleaving factors among different ranks has not yet been investigated. Furthermore, asynchronous SAR sub-ADCs are often used in these designs to push the sampling rate even further. The well-known sparkle-code issues caused by comparator meta-stability in asynchronous SARs can significantly increase the Bit-Error-Rate (BER) of the transceivers unless power hungry error correction coding are implemented in the system. Although many works in the literature attempted to deal with the meta-stability in asynchronous SARs, the effectiveness of these approaches have not been fully demonstrated. In this thesis, I will first propose a new cascode-based T&H circuits to improve the ADC bandwidth beyond the limit of conventional switch-based T&H circuits. Then, a system design and optimization methodology of hierarchical time-interleaved sampling network is presented in the context of cascode T&H. To deal with sparkle-code issue in asynchronous SAR sub-ADCs, a new back-end meta-stability correction technique is employed. An extensive statistical analysis is provided to verify the correction algorithm can greatly reduce sparkle-code error-rates. To further demonstrate the effectiveness of the proposed circuits and techniques, two prototype ADCs have been implemented. The first 7b 12.5GS/s hierarchically time-interleaved ADC in 65nm CMOS process demonstrates 29.4dB SNDR and >25GHz bandwidth. The later 6b 46GS/s ADC in 28nm CMOS employs asynchronous SAR sub-ADC design with back-end meta-stability correction. The measurement results show it achieves sparkle-code error free operation over 1e10 samples in addition to achieving >23GHz bandwidth and 25.2dB SNDR. The power consumption is 381mW from 1.05V/1.6V supplies, and the FOM is 0.56pJ/conversion-step.
High Performance And High Speed Pipelined Adcs
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Author : Manar El-Chammas
language : en
Publisher: Springer Nature
Release Date : 2023-05-19
High Performance And High Speed Pipelined Adcs written by Manar El-Chammas and has been published by Springer Nature this book supported file pdf, txt, epub, kindle and other format this book has been release on 2023-05-19 with Technology & Engineering categories.
This book discusses the theoretical foundations and design techniques needed to effectively design high-speed (multi-GS/s) and high-performance pipelined ADCs, which play a critical role in the signal chain of various systems. Readers will be walked through the design and analysis of pipelined ADCs and their topologies, and will learn both theoretical and practical design details that will enable them to explore and build these data converters. The author also presents details on various aspects of pipelined ADCs and their impact on the ADC speed and performance, with a focus on the input buffer and sampling network, the reference amplifier, comparators and their impact on ADC error rate and high-frequency performance, and mismatch estimation and correction.
Time Interleaved Analog To Digital Converters
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Author : Simon Louwsma
language : en
Publisher: Springer Science & Business Media
Release Date : 2010-09-08
Time Interleaved Analog To Digital Converters written by Simon Louwsma and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2010-09-08 with Technology & Engineering categories.
Time-interleaved Analog-to-Digital Converters describes the research performed on low-power time-interleaved ADCs. A detailed theoretical analysis is made of the time-interleaved Track & Hold, since it must be capable of handling signals in the GHz range with little distortion, and minimal power consumption. Timing calibration is not attractive, therefore design techniques are presented which do not require timing calibration. The design of power efficient sub-ADCs is addressed with a theoretical analysis of a successive approximation converter and a pipeline converter. It turns out that the first can consume about 10 times less power than the latter, and this conclusion is supported by literature. Time-interleaved Analog-to-Digital Converters describes the design of a high performance time-interleaved ADC, with much attention for practical design aspects, aiming at both industry and research. Measurements show best-inclass performance with a sample-rate of 1.8 GS/s, 7.9 ENOBs and a power efficiency of 1 pJ/conversion-step.
Calibration Of Sampling Clock Skew In High Speed High Resolution Time Interleaved Adcs
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Author : Daniel Prashanth Kumar
language : en
Publisher:
Release Date : 2015
Calibration Of Sampling Clock Skew In High Speed High Resolution Time Interleaved Adcs written by Daniel Prashanth Kumar and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2015 with categories.
There is an ever-increasing demand for high-resolution and high-resolution ADCs. In order to raise the sampling rates of ADCs in a power efficient manner, time-interleaving is an essential technique, whereby N ADC channels, each operating at a sampling frequency of fs, are used to achieve an effective conversion rate of N - fs. While time-interleaving enables higher conversion rates in a given technology, mismatch issues such as gain, offset, and sampling clock skew between channels degrade the overall time-interleaved ADC performance. Of these issues, sampling clock skew between channels is the biggest problem in high-speed and high-resolution, time-interleaved ADCs as errors due to sampling clock skew become more severe for higher input frequencies. There are a few sources of sampling clock skew between channels. Mismatches in the sampling clock path and logic delays are the most obvious ones. Input signal routing mismatch and RC mismatch of the input sampling circuits also cause sampling clock skew. In this thesis, we developed two new methods to mitigate the effects of sampling clock skew in time-interleaved ADCs. The first is the rapid consecutive sampling method, whereby each interleaved channel is implemented using two sub-channel ADCs. Two consecutive samples of the input are taken with a short time delay between them. This allows for a straight-forward linear interpolation between the consecutive samples in order to recover the de-skewed sample. The second method entails introducing a programmable delay in the input signal path, instead of delaying the sampling clock, in order to calibrate out sampling clock skew. The design and implementation of a proof-of-concept, time-interleaved ADC that implements the input signal delay method is detailed. Finally, measurement results to show the efficacy of the proposed method in mitigating the effects of sampling clock skew is also presented.
Techniques For Improving Timing Accuracy Of Multi Gigahertz Track Hold Circuits
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Author : Jingguang Wang
language : en
Publisher:
Release Date : 2009
Techniques For Improving Timing Accuracy Of Multi Gigahertz Track Hold Circuits written by Jingguang Wang and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2009 with Analog-to-digital converters categories.
Multi-Gigahertz sampling rate Analog-to-Digital Converters (ADC) with 5-8 bits resolution are used in many signal communication applications. Unfortunately, the performance of the high speed ADC is limited by the timing accuracy of the sampling clock. A small sampling uncertainty can cause a large error in the sampled voltage and result in harmonic distortions at the output. For different architectures of the T/H circuits, the timing error can arise from the clock random jitter or the phase skew among multi-phase clocks. For the ADC with global T/H circuits in front-end, an architecture with sine-wave sampling clock will be introduced that exhibits less random aperture jitter. First, the signal-dependent sampling error will be analyzed, and the comparison of the calculated and simulated results will be presented. Second, using the signal-to-distortion-ratio (SDR) simulations of a high speed NMOS T/H circuits with varying transition times of the sampling clock, we can compare the effects of the signal-dependent nonlinearity with other non-ideal effects. Based on the above analysis, a new architecture for multi-gigahertz sampling rate ADC using sine wave sampling will be introduced. For the ADC with time-interleaved T/Hs, a histogram based phase detector will be introduced to detect and calibrate the static timing error among the multi-channels. First, different timing error sources in high speed time-interleaved T/H will be analyzed. Second, a histogram based timing error detector will be proposed which not only cancels the skew in the multi-phase clocks but also the mismatch among different interleaved channels of the T/H circuits. An 8-channel 10GS/s T/H with timing error calibration has been implemented using IBM 90nm CMOS process. The static timing error before and after timing calibration will be presented from the measurement results.
Power Efficient High Speed Parallel Sampling Adcs For Broadband Multi Carrier Systems
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Author : Yu Lin
language : en
Publisher: Springer
Release Date : 2015-05-07
Power Efficient High Speed Parallel Sampling Adcs For Broadband Multi Carrier Systems written by Yu Lin and has been published by Springer this book supported file pdf, txt, epub, kindle and other format this book has been release on 2015-05-07 with Technology & Engineering categories.
This book addresses the challenges of designing high performance analog-to-digital converters (ADCs) based on the “smart data converters” concept, which implies context awareness, on-chip intelligence and adaptation. Readers will learn to exploit various information either a-priori or a-posteriori (obtained from devices, signals, applications or the ambient situations, etc.) for circuit and architecture optimization during the design phase or adaptation during operation, to enhance data converters performance, flexibility, robustness and power-efficiency. The authors focus on exploiting the a-priori knowledge of the system/application to develop enhancement techniques for ADCs, with particular emphasis on improving the power efficiency of high-speed and high-resolution ADCs for broadband multi-carrier systems.
Advanced Data Converters
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Author : Gabriele Manganaro
language : en
Publisher: Cambridge University Press
Release Date : 2011-11-17
Advanced Data Converters written by Gabriele Manganaro and has been published by Cambridge University Press this book supported file pdf, txt, epub, kindle and other format this book has been release on 2011-11-17 with Technology & Engineering categories.
Need to get up to speed quickly on the latest advances in high performance data converters? Want help choosing the best architecture for your application? With everything you need to know about the key new converter architectures, this guide is for you. It presents basic principles, circuit and system design techniques and associated trade-offs, doing away with lengthy mathematical proofs and providing intuitive descriptions upfront. Everything from time-to-digital converters to comparator-based/zero-crossing ADCs is covered and each topic is introduced with a short summary of the essential basics. Practical examples describing actual chips, along with extensive comparison between architectural or circuit options, ease architecture selection and help you cut design time and engineering risk. Trade-offs, advantages and disadvantages of each option are put into perspective with a discussion of future trends, showing where this field is heading, what is driving it and what the most important unanswered questions are.
Generalized Low Voltage Circuit Techniques For Very High Speed Time Interleaved Analog To Digital Converters
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Author : Sai-Weng Sin
language : en
Publisher: Springer Science & Business Media
Release Date : 2010-09-29
Generalized Low Voltage Circuit Techniques For Very High Speed Time Interleaved Analog To Digital Converters written by Sai-Weng Sin and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2010-09-29 with Technology & Engineering categories.
Analog-to-Digital Converters (ADCs) play an important role in most modern signal processing and wireless communication systems where extensive signal manipulation is necessary to be performed by complicated digital signal processing (DSP) circuitry. This trend also creates the possibility of fabricating all functional blocks of a system in a single chip (System On Chip - SoC), with great reductions in cost, chip area and power consumption. However, this tendency places an increasing challenge, in terms of speed, resolution, power consumption, and noise performance, in the design of the front-end ADC which is usually the bottleneck of the whole system, especially under the unavoidable low supply-voltage imposed by technology scaling, as well as the requirement of battery operated portable devices. Generalized Low-Voltage Circuit Techniques for Very High-Speed Time-Interleaved Analog-to-Digital Converters will present new techniques tailored for low-voltage and high-speed Switched-Capacitor (SC) ADC with various design-specific considerations.
Mismatch Calibration Techniques For Low Power High Speed Time Interleaved Adc
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Author : Ming Qiang Guo
language : en
Publisher:
Release Date : 2019
Mismatch Calibration Techniques For Low Power High Speed Time Interleaved Adc written by Ming Qiang Guo and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2019 with categories.