Timing Skew Calibration For Time Interleaved Analog To Digital Converters
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Timing Skew Calibration For Time Interleaved Analog To Digital Converters
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Author : Luke Wang
language : en
Publisher:
Release Date : 2014
Timing Skew Calibration For Time Interleaved Analog To Digital Converters written by Luke Wang and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2014 with categories.
Background Calibration Of Time Interleaved Data Converters
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Author : Manar El-Chammas
language : en
Publisher: Springer Science & Business Media
Release Date : 2011-12-17
Background Calibration Of Time Interleaved Data Converters written by Manar El-Chammas and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2011-12-17 with Technology & Engineering categories.
This book describes techniques for time-interleaving a number of analog-to-digital data converters to achieve demanding bandwidth requirements. Readers will benefit from the presentation of a low-power solution that can be used in actual products, while alleviating the time-varying signal artifacts that typically arise when implementing such a system architecture.
Background Calibration Of Timing Skew In Time Interleaved A D Converters
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Author : Manar Ibrahim El-Chammas
language : en
Publisher: Stanford University
Release Date : 2010
Background Calibration Of Timing Skew In Time Interleaved A D Converters written by Manar Ibrahim El-Chammas and has been published by Stanford University this book supported file pdf, txt, epub, kindle and other format this book has been release on 2010 with categories.
The increasing data rate of wireline communication systems leads to more inter-symbol interference, due to the dispersive properties of the communication channel. This requires more complex equalization blocks to meet the required bit-error rate. One solution is to use an Analog-to-Digital Converter (ADC) in the front-end, thus enabling a digitally-equalized serial link. To achieve the high-data rates of these communication systems, a time-interleaved ADC is typically used. However, this type of ADC suffers from several time-varying errors, the most prominent of which is timing skew. This thesis introduces a statistics-based background calibration algorithm that compensates for the effect of timing skew. To demonstrate the background calibration algorithm, a proof-of-concept 5 bit 12 GS/s flash ADC has been fabricated in a 65 nm CMOS process. The design of this ADC takes into consideration the tight power bounds imposed on serial links by optimizing both the time-interleaved and the sub-ADC architecture. Power consumption is further reduced by using calibration circuits to correct the offset of the flash ADC's comparators. In the measured results, the timing skew correction improves the dynamic performance of the time-interleaved ADC by 12 dB, and the proof-of-concept ADC has the lowest published power consumption for ADCs with sample rates higher than 10 GS/s.
Calibration Of Sampling Clock Skew In High Speed High Resolution Time Interleaved Adcs
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Author : Daniel Prashanth Kumar
language : en
Publisher:
Release Date : 2015
Calibration Of Sampling Clock Skew In High Speed High Resolution Time Interleaved Adcs written by Daniel Prashanth Kumar and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2015 with categories.
There is an ever-increasing demand for high-resolution and high-resolution ADCs. In order to raise the sampling rates of ADCs in a power efficient manner, time-interleaving is an essential technique, whereby N ADC channels, each operating at a sampling frequency of fs, are used to achieve an effective conversion rate of N - fs. While time-interleaving enables higher conversion rates in a given technology, mismatch issues such as gain, offset, and sampling clock skew between channels degrade the overall time-interleaved ADC performance. Of these issues, sampling clock skew between channels is the biggest problem in high-speed and high-resolution, time-interleaved ADCs as errors due to sampling clock skew become more severe for higher input frequencies. There are a few sources of sampling clock skew between channels. Mismatches in the sampling clock path and logic delays are the most obvious ones. Input signal routing mismatch and RC mismatch of the input sampling circuits also cause sampling clock skew. In this thesis, we developed two new methods to mitigate the effects of sampling clock skew in time-interleaved ADCs. The first is the rapid consecutive sampling method, whereby each interleaved channel is implemented using two sub-channel ADCs. Two consecutive samples of the input are taken with a short time delay between them. This allows for a straight-forward linear interpolation between the consecutive samples in order to recover the de-skewed sample. The second method entails introducing a programmable delay in the input signal path, instead of delaying the sampling clock, in order to calibrate out sampling clock skew. The design and implementation of a proof-of-concept, time-interleaved ADC that implements the input signal delay method is detailed. Finally, measurement results to show the efficacy of the proposed method in mitigating the effects of sampling clock skew is also presented.
Digital Calibration Of Double Sampled Time Interleaved Analog To Digital Converters
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Author : Chi Ho Law
language : en
Publisher:
Release Date : 2009
Digital Calibration Of Double Sampled Time Interleaved Analog To Digital Converters written by Chi Ho Law and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2009 with categories.
Digital Background Calibration Of Time Interleaved Analog To Digital Converters
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Author : Shafiq M. Jamal
language : en
Publisher:
Release Date : 2001
Digital Background Calibration Of Time Interleaved Analog To Digital Converters written by Shafiq M. Jamal and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2001 with Analog-to-digital converters categories.
2021 18th International Soc Design Conference Isocc
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Author : IEEE Staff
language : en
Publisher:
Release Date : 2021-10-06
2021 18th International Soc Design Conference Isocc written by IEEE Staff and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2021-10-06 with categories.
SoC, Analog Circuits, Digital Circuits, Data Converters, RF Microwave Wireless Circuits, Memories, Design Methodology, Circuits and Systems for Emerging Technologies, AI
Mismatch Calibration Of Time Interleaved Digital To Analog Converters
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Author : Rowena J. D'souza
language : en
Publisher:
Release Date : 2010
Mismatch Calibration Of Time Interleaved Digital To Analog Converters written by Rowena J. D'souza and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2010 with categories.
Time Interleaved Analog To Digital Converters For Digital Communications
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Author : Tsung-Heng Tsai
language : en
Publisher:
Release Date : 2005
Time Interleaved Analog To Digital Converters For Digital Communications written by Tsung-Heng Tsai and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2005 with categories.
Signal Reconstruction Algorithms For Time Interleaved Adcs
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Author : Anu Kalidas Muralidharan Pillai
language : en
Publisher: Linköping University Electronic Press
Release Date : 2015-05-22
Signal Reconstruction Algorithms For Time Interleaved Adcs written by Anu Kalidas Muralidharan Pillai and has been published by Linköping University Electronic Press this book supported file pdf, txt, epub, kindle and other format this book has been release on 2015-05-22 with Algorithms categories.
An analog-to-digital converter (ADC) is a key component in many electronic systems. It is used to convert analog signals to the equivalent digital form. The conversion involves sampling which is the process of converting a continuous-time signal to a sequence of discrete-time samples, and quantization in which each sampled value is represented using a finite number of bits. The sampling rate and the effective resolution (number of bits) are two key ADC performance metrics. Today, ADCs form a major bottleneck in many applications like communication systems since it is difficult to simultaneously achieve high sampling rate and high resolution. Among the various ADC architectures, the time-interleaved analog-to-digital converter (TI-ADC) has emerged as a popular choice for achieving very high sampling rates and resolutions. At the principle level, by interleaving the outputs of M identical channel ADCs, a TI-ADC could achieve the same resolution as that of a channel ADC but with M times higher bandwidth. However, in practice, mismatches between the channel ADCs result in a nonuniformly sampled signal at the output of a TI-ADC which reduces the achievable resolution. Often, in TIADC implementations, digital reconstructors are used to recover the uniform-grid samples from the nonuniformly sampled signal at the output of the TI-ADC. Since such reconstructors operate at the TI-ADC output rate, reducing the number of computations required per corrected output sample helps to reduce the power consumed by the TI-ADC. Also, as the mismatch parameters change occasionally, the reconstructor should support online reconfiguration with minimal or no redesign. Further, it is advantageous to have reconstruction schemes that require fewer coefficient updates during reconfiguration. In this thesis, we focus on reducing the design and implementation complexities of nonrecursive finite-length impulse response (FIR) reconstructors. We propose efficient reconstruction schemes for three classes of nonuniformly sampled signals that can occur at the output of TI-ADCs. Firstly, we consider a class of nonuniformly sampled signals that occur as a result of static timing mismatch errors or due to channel mismatches in TI-ADCs. For this type of nonuniformly sampled signals, we propose three reconstructors which utilize a two-rate approach to derive the corresponding single-rate structure. The two-rate based reconstructors move part of the complexity to a symmetric filter and also simplifies the reconstruction problem. The complexity reduction stems from the fact that half of the impulse response coefficients of the symmetric filter are equal to zero and that, compared to the original reconstruction problem, the simplified problem requires only a simpler reconstructor. Next, we consider the class of nonuniformly sampled signals that occur when a TI-ADC is used for sub-Nyquist cyclic nonuniform sampling (CNUS) of sparse multi-band signals. Sub-Nyquist sampling utilizes the sparsities in the analog signal to sample the signal at a lower rate. However, the reduced sampling rate comes at the cost of additional digital signal processing that is needed to reconstruct the uniform-grid sequence from the sub-Nyquist sampled sequence obtained via CNUS. The existing reconstruction scheme is computationally intensive and time consuming and offsets the gains obtained from the reduced sampling rate. Also, in applications where the band locations of the sparse multi-band signal can change from time to time, the reconstructor should support online reconfigurability. Here, we propose a reconstruction scheme that reduces the computational complexity of the reconstructor and at the same time, simplifies the online reconfigurability of the reconstructor. Finally, we consider a class of nonuniformly sampled signals which occur at the output of TI-ADCs that use some of the input sampling instants for sampling a known calibration signal. The samples corresponding to the calibration signal are used for estimating the channel mismatch parameters. In such TI-ADCs, nonuniform sampling is due to the mismatches between the channel ADCs and due to the missing input samples corresponding to the sampling instants reserved for the calibration signal. We propose three reconstruction schemes for such nonuniformly sampled signals and show using design examples that, compared to a previous solution, the proposed schemes require substantially lower computational complexity.