Modular Low Power High Speed Cmos Analog To Digital Converter Of Embedded Systems
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Modular Low Power High Speed Cmos Analog To Digital Converter Of Embedded Systems
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Author : Keh-La Lin
language : en
Publisher: Springer Science & Business Media
Release Date : 2006-01-14
Modular Low Power High Speed Cmos Analog To Digital Converter Of Embedded Systems written by Keh-La Lin and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2006-01-14 with Technology & Engineering categories.
One of the main trends of microelectronics is toward design for integrated systems, i.e., system-on-a-chip (SoC) or system-on-silicon (SoS). Due to this development, design techniques for mixed-signal circuits become more important than before. Among other devices, analog-to-digital and digital-to-analog converters are the two bridges between the analog and the digital worlds. Besides, low-power design technique is one of the main issues for embedded systems, especially for hand-held applications. Modular Low-Power, High-Speed CMOS Analog-to-Digital Converter for Embedded Systems aims at design techniques for low-power, high-speed analog-to-digital converter processed by the standard CMOS technology. Additionally this book covers physical integration issues of A/D converter integrated in SoC, i.e., substrate crosstalk and reference voltage network design.
Systematic Design Of Sigma Delta Analog To Digital Converters
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Author : Ovidiu Bajdechi
language : en
Publisher: Springer Science & Business Media
Release Date : 2004-04-30
Systematic Design Of Sigma Delta Analog To Digital Converters written by Ovidiu Bajdechi and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2004-04-30 with Computers categories.
Systematic Design of Sigma-Delta Analog-to-Digital Converters describes the issues related to the sigma-delta analog-to-digital converters (ADCs) design in a systematic manner: from the top level of abstraction represented by the filters defining signal and noise transfer functions (STF, NTF), passing through the architecture level where topology-related performance is calculated and simulated, and finally down to parameters of circuit elements like resistors, capacitors, and amplifier transconductances used in individual integrators. The systematic approach allows the evaluation of different loop filters (order, aggressiveness, discrete-time or continuous-time implementation) with quantizers varying in resolution. Topologies explored range from simple single loops to multiple cascaded loops with complex structures including more feedbacks and feedforwards. For differential circuits, with switched-capacitor integrators for discrete-time (DT) loop filters and active-RC for continuous-time (CT) ones, the passive integrator components are calculated and the power consumption is estimated, based on top-level requirements like harmonic distortion and noise budget. This unified, systematic approach to choosing the best sigma-delta ADC implementation for a given design target yields an interesting solution for a high-resolution, broadband (DSL-like) ADC operated at low oversampling ratio, which is detailed down to transistor-level schematics. The target audience of Systematic Design of Sigma-Delta Analog-to-Digital Converters are engineers designing sigma-delta ADCs and/or switched-capacitor and continuous-time filters, both beginners and experienced. It is also intended for students/academics involved in sigma-delta and analog CAD research.
Dynamic Characterisation Of Analogue To Digital Converters
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Author : Dominique Dallet
language : en
Publisher: Springer Science & Business Media
Release Date : 2006-03-08
Dynamic Characterisation Of Analogue To Digital Converters written by Dominique Dallet and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2006-03-08 with Technology & Engineering categories.
The Analogue-to-digital converter (ADC) is the most pervasive block in electronic systems. With the advent of powerful digital signal processing and digital communication techniques, ADCs are fast becoming critical components for system’s performance and flexibility. Knowing accurately all the parameters that characterise their dynamic behaviour is crucial, on one hand to select the most adequate ADC architecture and characteristics for each end application, and on the other hand, to understand how they affect performance bottlenecks in the signal processing chain. Dynamic Characterisation of Analogue-to-Digital Converters presents a state of the art overview of the methods and procedures employed for characterising ADCs’ dynamic performance behaviour using sinusoidal stimuli. The three classical methods – histogram, sine wave fitting, and spectral analysis – are thoroughly described, and new approaches are proposed to circumvent some of their limitations. This is a must-have compendium, which can be used by both academics and test professionals to understand the fundamental mathematics underlining the algorithms of ADC testing, and as an handbook to help the engineer in the most important and critical details for their implementation.
Low Power Analog Cmos For Cardiac Pacemakers
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Author : Fernando Silveira
language : en
Publisher: Springer Science & Business Media
Release Date : 2013-03-09
Low Power Analog Cmos For Cardiac Pacemakers written by Fernando Silveira and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2013-03-09 with Technology & Engineering categories.
Low Power Analog CMOS for Cardiac Pacemakers proposes new techniques for the reduction of power consumption in analog integrated circuits. Our main example is the pacemaker sense channel, which is representative of a broader class of biomedical circuits aimed at qualitatively detecting biological signals. The first and second chapters are a tutorial presentation on implantable medical devices and pacemakers from the circuit designer point of view. This is illustrated by the requirements and solutions applied in our implementation of an industrial IC for pacemakers. There from, the book discusses the means for reduction of power consumption at three levels: base technology, power-oriented analytical synthesis procedures and circuit architecture.
Low Power Deep Sub Micron Cmos Logic
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Author : P. van der Meer
language : en
Publisher: Springer Science & Business Media
Release Date : 2012-12-06
Low Power Deep Sub Micron Cmos Logic written by P. van der Meer and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2012-12-06 with Technology & Engineering categories.
1. 1 Power-dissipation trends in CMOS circuits Shrinking device geometry, growing chip area and increased data-processing speed performance are technological trends in the integrated circuit industry to enlarge chip functionality. Already in 1965 Gordon Moore predicted that the total number of devices on a chip would double every year until the 1970s and every 24 months in the 1980s. This prediction is widely known as "Moore's Law" and eventually culminated in the Semiconductor Industry Association (SIA) technology road map [1]. The SIA road map has been a guide for the in dustry leading them to continued wafer and die size growth, increased transistor density and operating frequencies, and defect density reduction. To mention a few numbers; the die size increased 7% per year, the smallest feature sizes decreased 30% and the operating frequencies doubled every two years. As a consequence of these trends both the number of transistors and the power dissi pation per unit area increase.In the near future the maximum power dissipation per unit area will be reached. Down-scaling of the supply voltage is not only the most effective way to reduce power dissipation in general it also is a necessary precondition to ensure device reliability by reducing electrical fields and device temperature, to prevent device degradation. A draw-back of this solution is an increased signal propa gation delay, which results in a lower data-processing speed performance.
Cmos Integrated Analog To Digital And Digital To Analog Converters
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Author : Rudy J. van de Plassche
language : en
Publisher: Springer Science & Business Media
Release Date : 2013-04-17
Cmos Integrated Analog To Digital And Digital To Analog Converters written by Rudy J. van de Plassche and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2013-04-17 with Technology & Engineering categories.
CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters describes in depth converter specifications like Effective Number of Bits (ENOB), Spurious Free Dynamic Range (SFDR), Integral Non-Linearity (INL), Differential Non-Linearity (DNL) and sampling clock jitter requirements. Relations between these specifications and practical issues like matching of components and offset parameters of differential pairs are derived. CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters describes the requirements of input and signal reconstruction filtering in case a converter is applied into a signal processing system. CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters describes design details of high-speed A/D and D/A converters, high-resolution A/D and D/A converters, sample-and-hold amplifiers, voltage and current references, noise-shaping converters and sigma-delta converters, technology parameters and matching performance, comparators and limitations of comparators and finally testing of converters.
Static And Dynamic Performance Limitations For High Speed D A Converters
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Author : Anne van den Bosch
language : en
Publisher: Springer Science & Business Media
Release Date : 2013-06-29
Static And Dynamic Performance Limitations For High Speed D A Converters written by Anne van den Bosch and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2013-06-29 with Technology & Engineering categories.
Static and Dynamic Performance Limitations for High Speed D/A Converters discusses the design and implementation of high speed current-steering CMOS digital-to-analog converters. Starting from the definition of the basic specifications for a D/A converter, the elements determining the static and dynamic performance are identified. Different guidelines based on scientific derivations are suggested to optimize this performance. Furthermore, a new closed formula has been derived to account for the influence of the transistor mismatch on the achievable resolution of the current-steering D/A converter. To allow a thorough understanding of the dynamic behavior, a new factor has been introduced. Moreover, the frequency dependency of the output impedance introduces harmonic distortion components which can limit the maximum attainable spurious free dynamic range. Finally, the last part of the book gives an overview on different existing transistor mismatch models and the link with the static performance of the D/A converter.
Low Voltage Cmos Log Companding Analog Design
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Author : Francisco Serra-Graells
language : en
Publisher: Springer Science & Business Media
Release Date : 2006-04-18
Low Voltage Cmos Log Companding Analog Design written by Francisco Serra-Graells and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2006-04-18 with Technology & Engineering categories.
Low-Voltage CMOS Log Companding Analog Design presents in detail state-of-the-art analog circuit techniques for the very low-voltage and low-power design of systems-on-chip in CMOS technologies. The proposed strategy is mainly based on two bases: the Instantaneous Log Companding Theory, and the MOSFET operating in the subthreshold region. The former allows inner compression of the voltage dynamic-range for very low-voltage operation, while the latter is compatible with CMOS technologies and suitable for low-power circuits. The required background on the specific modeling of the MOS transistor for Companding is supplied at the beginning. Following this general approach, a complete set of CMOS basic building blocks is proposed and analyzed for a wide variety of analog signal processing. In particular, the covered areas include: amplification and AGC, arbitrary filtering, PTAT generation, and pulse duration modulation (PDM). For each topic, several case studies areconsidered to illustrate the design methodology. Also, integrated examples in 1.2um and 0.35um CMOS technologies are reported to verify the good agreement between design equations and experimental data. The resulting analog circuit topologies exhibit very low-voltage (i.e. 1V) and low-power (few tenths of uA) capabilities. Apart from these specific design examples, a real industrial application in the field of hearing aids is also presented as the main demonstrator of all the proposed basic building blocks. This system-on-chip exhibits true 1V operation, high flexibility through digital programmability and very low-power consumption (about 300uA including the Class-D amplifier). As a result, the reported ASIC can meet the specifications of a complete family of common hearing aid models. In conclusion, this book is addressed to both industry ASIC designers who can apply its contents to the synthesis of very low-power systems-on-chip in standard CMOS technologies, as wellas to the teachers of modern circuit design in electronic engineering.
Design Of Low Voltage Cmos Switched Opamp Switched Capacitor Systems
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Author : Vincent S.L. Cheung
language : en
Publisher: Springer Science & Business Media
Release Date : 2013-03-14
Design Of Low Voltage Cmos Switched Opamp Switched Capacitor Systems written by Vincent S.L. Cheung and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2013-03-14 with Technology & Engineering categories.
In Design of Low-Voltage CMOS Switched-Opamp Switched-Capacitor Systems, the emphasis is put on the design and development of advanced switched-opamp architectures and techniques for low-voltage low-power switched-capacitor (SC) systems. Specifically, the book presents a novel multi-phase switched-opamp technique together with new system architectures that are critical in improving significantly the performance of switched-capacitor systems at low supply voltages: *A generic fast-settling double-sampling SC biquadratic filter architecture is proposed to achieve high-speed operation for SC circuits. *A low-voltage double-sampling (DS) finite-gain-compensation (FGC) technique is employed to realize high-resolution SD modulator using only low-DC-gain opamps to maximize the speed and to reduce power dissipation. *A family of novel power-efficient SC filters and SD modulators are built based on using only half-delay SC integrators. *Single-opamp-based SCsystems are designed for ultra-low-power applications. In addition, on the circuit level, a fast-switching methodology is proposed for the design of the switchable opamps to achieve switching frequency up to 50 MHz at 1V, which is improved by about ten times compared to the prior arts. Finally, detailed design considerations, architecture choices, and circuit implementation of five chip prototypes are presented to illustrate potential applications of the proposed multi-phase switched-opamp technique to tackle with and to achieve different stringent design corners such as high-speed, high-integration-level and ultra-low-power consumption at supply voltages of 1V or lower in standard CMOS processes.
Design Of Very High Frequency Multirate Switched Capacitor Circuits
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Author : Seng-Pan U
language : en
Publisher: Springer Science & Business Media
Release Date : 2006
Design Of Very High Frequency Multirate Switched Capacitor Circuits written by Seng-Pan U and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2006 with Computers categories.
Design of Very High-Frequency Multirate Switched-Capacitor Circuits presents the theory and the corresponding CMOS implementation of the novel multirate sampled-data analog interpolation technique which has its great potential on very high-frequency analog frond-end filtering due to its inherent dual advantage of reducing the speed of data-converters and DSP core together with the specification relaxation of the post continuous-time filtering. This technique completely eliminates the traditional phenomenon of sampled-and-hold frequency-shaping at the lower input sampling rate. Also, in order to tackle physical IC imperfections at very high frequency, the state-of-the-art circuit design and layout techniques for high-speed Switched-Capacitor (SC) circuits are comprehensively discussed: -Optimum circuit architecture tradeoff analysis -Simple speed and power trade-off analysis of active elements -High-order filtering response accuracy with respect to capacitor-ratio mismatches -Time-interleaved effect with respect to gain and offset mismatch -Time-interleaved effect with respect to timing-skew and random jitter with non-uniformly holding -Stage noise analysis and allocation scheme -Substrate and supply noise reduction -Gain-and offset-compensation techniques -High-bandwidth low-power amplifier design and layout -Very low timing-skew multiphase generation Two tailor-made optimum design examples in CMOS are presented. The first one achieves a 3-stage 8-fold SC interpolating filter with 5.5MHz bandwidth and 108MHz output sampling rate for a NTSC/PAL CCIR 601 digital video at 3 V. Another is a 15-tap 57MHz SC FIR bandpass interpolating filter with 4-fold sampling rate increase to 320MHz and the first-time embedded frequency band up-translation for DDFS system at 2.5V. The corresponding chip prototype achieves so far the highest operating frequency, highest filter order and highest center frequency with highest dynamic range under the lowest supply voltage when compared to the previously reported high-frequency SC filters in CMOS.