Performance Modeling And Optimization Techniques In The Presence Of Random Process Variations To Improve Parametric Yield Of Vlsi Circuits
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Performance Modeling And Optimization Techniques In The Presence Of Random Process Variations To Improve Parametric Yield Of Vlsi Circuits
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Author : Shubhankar Basu
language : en
Publisher:
Release Date : 2008
Performance Modeling And Optimization Techniques In The Presence Of Random Process Variations To Improve Parametric Yield Of Vlsi Circuits written by Shubhankar Basu and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2008 with categories.
As semiconductor industry continues to follow Moore's Law of doubled device count every 18 months, it is challenged by the rising uncertainties in the manufacturing process for nanometer technologies. Manufacturing defects lead to a random variation in physical parameters like the dopant density, critical dimensions and oxide thickness. These physical defects manifest themselves as variations in device process parameters like threshold voltage and effective channel length of transistors. The randomness in process parameters affect the performance of VLSI circuits which leads to a loss in parametric yield. Conventional design methodologies, with corner case based analysis techniques fail to predict the performance of circuits reliably in the presence of random process variations. Moreover, the analysis techniques for detection of defects in the later stages of the design cycle result in significant overhead in cost due to re-spins. In recent times, VLSI computer aided design methodologies have shifted to statistical analysis techniques for performance measurements with specific yield targets. However, the adoption of statistical techniques in commercial design flows has been limited by the complexity of their usage and the need for generating specially characterized models. This also makes them unsuitable in repeated loops during the synthesis process. In this dissertation, we present an alternate approach to model and optimize the performance of digital and analog circuits in the presence of random process variations. Our work is targeted for a bottom-up methodology providing incremental tolerance to the circuits under the impact of random process variations. The methodologies presented, can be used to generate fast evaluating accurate macromodels to compute the bounds of performance due to the underlying variations in device parameters. The primary goal of our methodology is to capture the statistical aspects of variation in the lower levels of abstraction, while aiding deterministic analysis during the top level design optimization. We also attempt to build our solutions as a wrapper around a conventional design flow, without the requirement for special characterization. The modeling and optimization techniques are perfectly scalable across technology generations and can find practical usage during variation-tolerant synthesis of VLSI circuit performance.
Statistical Analysis And Optimization For Vlsi Timing And Power
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Author : Ashish Srivastava
language : en
Publisher: Springer Science & Business Media
Release Date : 2006-04-04
Statistical Analysis And Optimization For Vlsi Timing And Power written by Ashish Srivastava and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2006-04-04 with Technology & Engineering categories.
Covers the statistical analysis and optimization issues arising due to increased process variations in current technologies. Comprises a valuable reference for statistical analysis and optimization techniques in current and future VLSI design for CAD-Tool developers and for researchers interested in starting work in this very active area of research. Written by author who lead much research in this area who provide novel ideas and approaches to handle the addressed issues
Parametric Yield Of Vlsi Systems Under Variability
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Author : Kian Haghdad
language : en
Publisher:
Release Date : 2011
Parametric Yield Of Vlsi Systems Under Variability written by Kian Haghdad and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2011 with categories.
Variability has become one of the vital challenges that the designers of integrated circuits encounter. variability becomes increasingly important. Imperfect manufacturing process manifest itself as variations in the design parameters. These variations and those in the operating environment of VLSI circuits result in unexpected changes in the timing, power, and reliability of the circuits. With scaling transistor dimensions, process and environmental variations become significantly important in the modern VLSI design. A smaller feature size means that the physical characteristics of a device are more prone to these unaccounted-for changes. To achieve a robust design, the random and systematic fluctuations in the manufacturing process and the variations in the environmental parameters should be analyzed and the impact on the parametric yield should be addressed. This thesis studies the challenges and comprises solutions for designing robust VLSI systems in the presence of variations. Initially, to get some insight into the system design under variability, the parametric yield is examined for a small circuit. Understanding the impact of variations on the yield at the circuit level is vital to accurately estimate and optimize the yield at the system granularity. Motivated by the observations and results, found at the circuit level, statistical analyses are performed, and solutions are proposed, at the system level of abstraction, to reduce the impact of the variations and increase the parametric yield. At the circuit level, the impact of the supply and threshold voltage variations on the parametric yield is discussed. Here, a design centering methodology is proposed to maximize the parametric yield and optimize the power-performance trade-off under variations. In addition, the scaling trend in the yield loss is studied. Also, some considerations for design centering in the current and future CMOS technologies are explored. The investigation, at the circuit level, suggests that the operating temperature significantly affects the parametric yield. In addition, the yield is very sensitive to the magnitude of the variations in supply and threshold voltage. Therefore, the spatial variations in process and environmental variations make it necessary to analyze the yield at a higher granularity. Here, temperature and voltage variations are mapped across the chip to accurately estimate the yield loss at the system level. At the system level, initially the impact of process-induced temperature variations on the power grid design is analyzed. Also, an efficient verification method is provided that ensures the robustness of the power grid in the presence of variations. Then, a statistical analysis of the timing yield is conducted, by taking into account both the process and environmental variations. By considering the statistical profile of the temperature and supply voltage, the process variations are mapped to the delay variations across a die. This ensures an accurate estimation of the timing yield. In addition, a method is proposed to accurately estimate the power yield considering process-induced temperature and supply voltage variations. This helps check the robustness of the circuits early in the design process. Lastly, design solutions are presented to reduce the power consumption and increase the timing yield under the variations. In the first solution, a guideline for floorplaning optimization in the presence of temperature variations is offered. Non-uniformity in the thermal profiles of integrated circuits is an issue that impacts the parametric yield and threatens chip reliability. Therefore, the correlation between the total power consumption and the temperature variations across a chip is examined. As a result, floorplanning guidelines are proposed that uses the correlation to efficiently optimize the chip's total power and takes into account the thermal uniformity. The second design solution provides an optimization methodology for assigning the power supply pads across the chip for maximizing the timing yield. A mixed-integer nonlinear programming (MINLP) optimization problem, subject to voltage drop and current constraint, is efficiently solved to find the optimum number and location of the pads.
Dissertation Abstracts International
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Author :
language : en
Publisher:
Release Date : 2009
Dissertation Abstracts International written by and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2009 with Dissertations, Academic categories.
Statistical Approach To Vlsi
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Author : Stephen W. Director
language : en
Publisher: North Holland
Release Date : 1994
Statistical Approach To Vlsi written by Stephen W. Director and has been published by North Holland this book supported file pdf, txt, epub, kindle and other format this book has been release on 1994 with Computers categories.
This volume is the first complete overview of VLSI design methods that use statistical techniques for dealing with the random phenomena that are inherent in all VLSI manufacturing processes. VLSI design today cannot be performed without taking into account economic-related issues such as yield, cost and performance oriented tradeoffs. The book includes practical methods relevant to real life applications. It contains edited papers by top industrial and academic specialists in the field. These papers describe all three categories of CAD tools employed for statistical design: IC performance optimization tools, process simulation tools and tools for characterization of process fluctuations. In each category both practical approaches and more theoretical approaches are presented.
Statistical Modeling For Computer Aided Design Of Mos Vlsi Circuits
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Author : Christopher Michael
language : en
Publisher: Springer Science & Business Media
Release Date : 1993-01-31
Statistical Modeling For Computer Aided Design Of Mos Vlsi Circuits written by Christopher Michael and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 1993-01-31 with Computers categories.
As MOS devices are scaled to meet increasingly demanding circuit specifications, process variations have a greater effect on the reliability of circuit performance. For this reason, statistical techniques are required to design integrated circuits with maximum yield. Statistical Modeling for Computer-Aided Design of MOS VLSI Circuits describes a statistical circuit simulation and optimization environment for VLSI circuit designers. The first step toward accomplishing statistical circuit design and optimization is the development of an accurate CAD tool capable of performing statistical simulation. This tool must be based on a statistical model which comprehends the effect of device and circuit characteristics, such as device size, bias, and circuit layout, which are under the control of the circuit designer on the variability of circuit performance. The distinctive feature of the CAD tool described in this book is its ability to accurately model and simulate the effect in both intra- and inter-die process variability on analog/digital circuits, accounting for the effects of the aforementioned device and circuit characteristics. Statistical Modeling for Computer-Aided Design of MOS VLSI Circuits serves as an excellent reference for those working in the field, and may be used as the text for an advanced course on the subject.
Statistical Performance Analysis And Modeling Techniques For Nanometer Vlsi Designs
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Author : Ruijing Shen
language : en
Publisher: Springer Science & Business Media
Release Date : 2014-07-08
Statistical Performance Analysis And Modeling Techniques For Nanometer Vlsi Designs written by Ruijing Shen and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2014-07-08 with Technology & Engineering categories.
Since process variation and chip performance uncertainties have become more pronounced as technologies scale down into the nanometer regime, accurate and efficient modeling or characterization of variations from the device to the architecture level have become imperative for the successful design of VLSI chips. This book provides readers with tools for variation-aware design methodologies and computer-aided design (CAD) of VLSI systems, in the presence of process variations at the nanometer scale. It presents the latest developments for modeling and analysis, with a focus on statistical interconnect modeling, statistical parasitic extractions, statistical full-chip leakage and dynamic power analysis considering spatial correlations, statistical analysis and modeling for large global interconnects and analog/mixed-signal circuits. Provides readers with timely, systematic and comprehensive treatments of statistical modeling and analysis of VLSI systems with a focus on interconnects, on-chip power grids and clock networks, and analog/mixed-signal circuits; Helps chip designers understand the potential and limitations of their design tools, improving their design productivity; Presents analysis of each algorithm with practical applications in the context of real circuit design; Includes numerical examples for the quantitative analysis and evaluation of algorithms presented. Provides readers with timely, systematic and comprehensive treatments of statistical modeling and analysis of VLSI systems with a focus on interconnects, on-chip power grids and clock networks, and analog/mixed-signal circuits; Helps chip designers understand the potential and limitations of their design tools, improving their design productivity; Presents analysis of each algorithm with practical applications in the context of real circuit design; Includes numerical examples for the quantitative analysis and evaluation of algorithms presented.
Yield And Variability Optimization Of Integrated Circuits
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Author : Jian Cheng Zhang
language : en
Publisher: Springer Science & Business Media
Release Date : 2013-03-09
Yield And Variability Optimization Of Integrated Circuits written by Jian Cheng Zhang and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2013-03-09 with Technology & Engineering categories.
Traditionally, Computer Aided Design (CAD) tools have been used to create the nominal design of an integrated circuit (IC), such that the circuit nominal response meets the desired performance specifications. In reality, however, due to the disturbances ofthe IC manufacturing process, the actual performancesof the mass produced chips are different than those for the nominal design. Even if the manufacturing process were tightly controlled, so that there were little variations across the chips manufactured, the environmentalchanges (e. g. those oftemperature, supply voltages, etc. ) would alsomakethe circuit performances vary during the circuit life span. Process-related performance variations may lead to low manufacturing yield, and unacceptable product quality. For these reasons, statistical circuit design techniques are required to design the circuit parameters, taking the statistical process variations into account. This book deals with some theoretical and practical aspects of IC statistical design, and emphasizes how they differ from those for discrete circuits. It de scribes a spectrum of different statistical design problems, such as parametric yield optimization, generalized on-target design, variability minimization, per formance tunning, and worst-case design. The main emphasis of the presen tation is placed on the principles and practical solutions for performance vari ability minimization. It is hoped that the book may serve as an introductory reference material for various groups of IC designers, and the methodologies described will help them enhance the circuit quality and manufacturability. The book containsseven chapters.
Techniques For Vlsi Circuit Optimization Considering Process Variations
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Author : Mahalingam Venkataraman
language : en
Publisher:
Release Date : 2009
Techniques For Vlsi Circuit Optimization Considering Process Variations written by Mahalingam Venkataraman and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2009 with categories.
ABSTRACT: Technology scaling has increased the transistor's susceptibility to process variations in nanometer very large scale integrated (VLSI) circuits. The effects of such variations are having a huge impact on performance and hence the timing yield of the integrated circuits. The circuit optimization objectives namely power, area, and delay are highly correlated and conflicting in nature. The inception of variations in process parameters have made their relationship intricate and more difficult to optimize. Traditional deterministic methods ignoring variation effects negatively impacts timing yield. A pessimistic worst case consideration of variations, on the other hand, can lead to severe over design. In this context, there is a strong need for re-invention of circuit optimization methods with a statistical perspective. In this dissertation, we model and develop novel variation aware solutions for circuit optimization methods such as gate sizing, timing based placement and buffer insertion. The uncertainty due to process variations is modeled using interval valued fuzzy numbers and a fuzzy programming based optimization is proposed to improve circuit yield without significant over design. In addition to the statistical optimization methods, we have proposed a novel technique that dynamically detects and creates the slack needed to accommodate the delay due to variations. The variation aware gate sizing technique is formulated as a fuzzy linear program and the uncertainty in delay due to process variations is modeled using fuzzy membership functions. The timing based placement technique, on the other hand, due to its quadratic dependence on wire length is modeled as nonlinear programming problem. The variations in timing based placement are modeled as fuzzy numbers in the fuzzy formulation and as chance constraints in the stochastic formulation. Further, we have proposed a piece-wise linear formulation for the variation aware buffer insertion and driver sizing (BIDS) problem. The BIDS problem is solved at the logic level, with look-up table based approximation of net lengths for early variation awareness. In the context of dynamic variation compensation, a delay detection circuit is used to identify the uncertainty in critical path delay. The delay detection circuit controls the instance of data capture in critical path memory flops to avoid a timing failure in the presence of variations. In summary, the various formulation and solution techniques developed in this dissertation achieve significantly better optimization compared to related works in the literature. The proposed methods have been rigorously tested on medium and large sized benchmarks to establish the validity and efficacy of the solution techniques.
Statistical Analysis And Optimization For Vlsi Timing And Power
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Author : Ashish Srivastava
language : en
Publisher: Springer
Release Date : 2008-11-01
Statistical Analysis And Optimization For Vlsi Timing And Power written by Ashish Srivastava and has been published by Springer this book supported file pdf, txt, epub, kindle and other format this book has been release on 2008-11-01 with Technology & Engineering categories.
Covers the statistical analysis and optimization issues arising due to increased process variations in current technologies. Comprises a valuable reference for statistical analysis and optimization techniques in current and future VLSI design for CAD-Tool developers and for researchers interested in starting work in this very active area of research. Written by author who lead much research in this area who provide novel ideas and approaches to handle the addressed issues
