A Unified Approach For Timing Verification And Delay Fault Testing
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A Unified Approach For Timing Verification And Delay Fault Testing
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Author : Mukund Sivaraman
language : en
Publisher: Springer Science & Business Media
Release Date : 2012-09-17
A Unified Approach For Timing Verification And Delay Fault Testing written by Mukund Sivaraman and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2012-09-17 with Technology & Engineering categories.
Large system complexities and operation under tight timing constraints in rapidly shrinking technologies have made it extremely important to ensure correct temporal behavior of modern-day digital circuits, both before and after fabrication. Research in (pre-fabrication) timing verification and (post-fabrication) delay fault testing has evolved along largely disjoint lines in spite of the fact that they share many basic concepts. A Unified Approach for Timing Verification and Delay Fault Testing applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. A new path sensitization strategy called Signal Stabilization Time Analysis (SSTA) has been developed based on the fact that primitive PDFs determine the stabilization time of the circuit outputs. This analysis has been used to develop a feasible method of identifying the primitive PDFs in a general multi-level logic circuit. An approach to determine the maximum circuit delay using this primitive PDF identification mechanism is also presented. The Primitive PDF Identification-based Timing Analysis (PITA) approach is proved to determine the maximum floating mode circuit delay exactly under any component delay model, and provides several advantages over previously floating mode timing analyzers. A framework for the diagnosis of circuit failures caused by distributed path delay faults is also presented. A metric to quantify the diagnosability of a path delay fault for a test is also proposed. Finally, the book presents a very realistic metric for delay fault coverage which accounts for delay fault size distributions and is applicable to any delay fault model. A Unified Approach for Timing Verification and Delay Fault Testing will be of interest to university and industry researchers in timing analysis and delay fault testing as well as EDA tool development engineers and design verification engineers dealing with timing issues in ULSI circuits. The book should also be of interest to digital designers and others interested in knowing the state of the art in timing verification and delay fault testing.
Delay Fault Testing For Vlsi Circuits
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Author : Angela Krstic
language : en
Publisher: Springer Science & Business Media
Release Date : 2012-12-06
Delay Fault Testing For Vlsi Circuits written by Angela Krstic and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2012-12-06 with Technology & Engineering categories.
In the early days of digital design, we were concerned with the logical correctness of circuits. We knew that if we slowed down the clock signal sufficiently, the circuit would function correctly. With improvements in the semiconductor process technology, our expectations on speed have soared. A frequently asked question in the last decade has been how fast can the clock run. This puts significant demands on timing analysis and delay testing. Fueled by the above events, a tremendous growth has occurred in the research on delay testing. Recent work includes fault models, algorithms for test generation and fault simulation, and methods for design and synthesis for testability. The authors of this book, Angela Krstic and Tim Cheng, have personally contributed to this research. Now they do an even greater service to the profession by collecting the work of a large number of researchers. In addition to expounding such a great deal of information, they have delivered it with utmost clarity. To further the reader's understanding many key concepts are illustrated by simple examples. The basic ideas of delay testing have reached a level of maturity that makes them suitable for practice. In that sense, this book is the best x DELAY FAULT TESTING FOR VLSI CIRCUITS available guide for an engineer designing or testing VLSI systems. Tech niques for path delay testing and for use of slower test equipment to test high-speed circuits are of particular interest.
Dependable Multicore Architectures At Nanoscale
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Author : Marco Ottavi
language : en
Publisher: Springer
Release Date : 2017-08-28
Dependable Multicore Architectures At Nanoscale written by Marco Ottavi and has been published by Springer this book supported file pdf, txt, epub, kindle and other format this book has been release on 2017-08-28 with Technology & Engineering categories.
This book provides comprehensive coverage of the dependability challenges in today's advanced computing systems. It is an in-depth discussion of all the technological and design-level techniques that may be used to overcome these issues and analyzes various dependability-assessment methods. The impact of individual application scenarios on the definition of challenges and solutions is considered so that the designer can clearly assess the problems and adjust the solution based on the specifications in question. The book is composed of three sections, beginning with an introduction to current dependability challenges arising in complex computing systems implemented with nanoscale technologies, and of the effect of the application scenario. The second section details all the fault-tolerance techniques that are applicable in the manufacture of reliable advanced computing devices. Different levels, from technology-level fault avoidance to the use of error correcting codes and system-level checkpointing are introduced and explained as applicable to the different application scenario requirements. Finally the third section proposes a roadmap of future trends in and perspectives on the dependability and manufacturability of advanced computing systems from the special point of view of industrial stakeholders. Dependable Multicore Architectures at Nanoscale showcases the original ideas and concepts introduced into the field of nanoscale manufacturing and systems reliability over nearly four years of work within COST Action IC1103 MEDIAN, a think-tank with participants from 27 countries. Academic researchers and graduate students working in multi-core computer systems and their manufacture will find this book of interest as will industrial design and manufacturing engineers working in VLSI companies.
Essentials Of Electronic Testing For Digital Memory And Mixed Signal Vlsi Circuits
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Author : M. Bushnell
language : en
Publisher: Springer Science & Business Media
Release Date : 2006-04-11
Essentials Of Electronic Testing For Digital Memory And Mixed Signal Vlsi Circuits written by M. Bushnell and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2006-04-11 with Technology & Engineering categories.
The modern electronic testing has a forty year history. Test professionals hold some fairly large conferences and numerous workshops, have a journal, and there are over one hundred books on testing. Still, a full course on testing is offered only at a few universities, mostly by professors who have a research interest in this area. Apparently, most professors would not have taken a course on electronic testing when they were students. Other than the computer engineering curriculum being too crowded, the major reason cited for the absence of a course on electronic testing is the lack of a suitable textbook. For VLSI the foundation was provided by semiconductor device techn- ogy, circuit design, and electronic testing. In a computer engineering curriculum, therefore, it is necessary that foundations should be taught before applications. The field of VLSI has expanded to systems-on-a-chip, which include digital, memory, and mixed-signalsubsystems. To our knowledge this is the first textbook to cover all three types of electronic circuits. We have written this textbook for an undergraduate “foundations” course on electronic testing. Obviously, it is too voluminous for a one-semester course and a teacher will have to select from the topics. We did not restrict such freedom because the selection may depend upon the individual expertise and interests. Besides, there is merit in having a larger book that will retain its usefulness for the owner even after the completion of the course. With equal tenacity, we address the needs of three other groups of readers.
A Designer S Guide To Built In Self Test
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Author : Charles E. Stroud
language : en
Publisher: Springer Science & Business Media
Release Date : 2005-12-27
A Designer S Guide To Built In Self Test written by Charles E. Stroud and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2005-12-27 with Technology & Engineering categories.
A recent technological advance is the art of designing circuits to test themselves, referred to as a Built-In Self-Test. This book is written from a designer's perspective and describes the major BIST approaches that have been proposed and implemented, along with their advantages and limitations.
Signal Stabilization Analysis For Timing Verification And Delay Fault Testing
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Author : Mukund Sivaraman
language : en
Publisher:
Release Date : 1997
Signal Stabilization Analysis For Timing Verification And Delay Fault Testing written by Mukund Sivaraman and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 1997 with Electronic circuit design categories.
Abstract: "Present-day digital systems are characterized by large complexity, operation under tight timing constraints, numerous false paths, and large variations in component delays. In such a scenario, it is very important to ensure correct temporal behavior of these circuits, both before and after fabrication. For combinational circuits, it has been shown that it is necessary and sufficient to guarantee that the primitive path delay faults (primitive PDFs) are fault-free to ensure that the circuit operates correctly for some timing constraint T and all larger timing constraints, where primitive PDFs correspond to minimal sets of paths that are singly/jointly non-robustly testable. We show that primitive PDFs determine the stabilization time of the circuit outputs, based on which we develop a feasible method to identify the primitive PDFs in a general multilevel logic circuit. We also develop an approach to determine the maximum circuit delay using this primitive PDF identification mechanism, and prove that this delay is exactly equal to the maximum circuit delay found under the floating mode of operation assumption. Our timing analysis approach provides several advantages over previously reported floating mode timing analyzers: increased accuracy in the presence of component delay correlations and signal correlations arising from fabrication process, signal propagation, and signal interaction effects; increased efficiency in situations where critical paths need to be re- identified due to component delay speedup (e.g., post-layout delay optimization). We also present a framework for the diagnosis of circuit failures caused by distributed path delay faults. This involves determining the paths/sub-paths and fabrication process parameters that caused the chip failure. A metric to quantify the diagnosability of a path delay fault for a test is also proposed. Finally, we propose a very realistic metric for delay fault coverage which accounts for delay fault size distributions and is applicable to any delay fault model. We apply this metric to estimate the true delay fault coverage of robust test sets."
Timing Verification Of Application Specific Integrated Circuits Asics
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Author : Farzad Nekoogar
language : en
Publisher:
Release Date : 1999
Timing Verification Of Application Specific Integrated Circuits Asics written by Farzad Nekoogar and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 1999 with Computers categories.
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Principles Of Testing Electronic Systems
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Author : Samiha Mourad
language : en
Publisher: John Wiley & Sons
Release Date : 2000-07-25
Principles Of Testing Electronic Systems written by Samiha Mourad and has been published by John Wiley & Sons this book supported file pdf, txt, epub, kindle and other format this book has been release on 2000-07-25 with Technology & Engineering categories.
A pragmatic approach to testing electronic systems As we move ahead in the electronic age, rapid changes in technology pose an ever-increasing number of challenges in testing electronic products. Many practicing engineers are involved in this arena, but few have a chance to study the field in a systematic way-learning takes place on the job. By covering the fundamental disciplines in detail, Principles of Testing Electronic Systems provides design engineers with the much-needed knowledge base. Divided into five major parts, this highly useful reference relates design and tests to the development of reliable electronic products; shows the main vehicles for design verification; examines designs that facilitate testing; and investigates how testing is applied to random logic, memories, FPGAs, and microprocessors. Finally, the last part offers coverage of advanced test solutions for today's very deep submicron designs. The authors take a phenomenological approach to the subject matter while providing readers with plenty of opportunities to explore the foundation in detail. Special features include: * An explanation of where a test belongs in the design flow * Detailed discussion of scan-path and ordering of scan-chains * BIST solutions for embedded logic and memory blocks * Test methodologies for FPGAs * A chapter on testing system on a chip * Numerous references
Test And Diagnosis For Small Delay Defects
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Author : Mohammad Tehranipoor
language : en
Publisher: Springer Science & Business Media
Release Date : 2011-09-08
Test And Diagnosis For Small Delay Defects written by Mohammad Tehranipoor and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2011-09-08 with Technology & Engineering categories.
This book will introduce new techniques for detecting and diagnosing small-delay defects in integrated circuits. Although this sort of timing defect is commonly found in integrated circuits manufactured with nanometer technology, this will be the first book to introduce effective and scalable methodologies for screening and diagnosing small-delay defects, including important parameters such as process variations, crosstalk, and power supply noise.
Hierarchical Timing Verification And Delay Fault Testing
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Author : Rathish Jayabharathi
language : en
Publisher:
Release Date : 1999
Hierarchical Timing Verification And Delay Fault Testing written by Rathish Jayabharathi and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 1999 with Integrated circuits categories.