Low Power Design Techniques For High Speed Pipelined Adcs

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Low Power Design Techniques For High Speed Pipelined Adcs

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Author : Naga Sasidhar Lingam
language : en
Publisher:
Release Date : 2009

Low Power Design Techniques For High Speed Pipelined Adcs written by Naga Sasidhar Lingam and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2009 with Low voltage integrated circuits categories.

Real world is analog but the processing of signals can best be done in digital domain. So the need for Analog to Digital Converters (ADCs) is ever rising as more and more applications set in. With the advent of mobile technology, power in electronic equipment is being driven down to get more battery life. Because of their ubiquitous nature, ADCs are prime blocks in the signal chain in which power is intended to be reduced. In this thesis, four techniques to reduce power in high speed pipelined ADCs have been proposed. The first is a capacitor and opamp sharing technique that reduces the load on the first stage opamp by three fold. The second is a capacitor reset technique that aids removing the sample and hold block to reduce power. The third is a modified MDAC which can take rail-to-rail input swing to get an extra bit thus getting rid of a power hungry opamp. The fourth is a hybrid architecture which makes use of an asynchronous SAR ADC as the backend of a pipelined ADC to save power. Measurement and simulation results that prove the efficiency of the proposed techniques are presented.

Pipelined Adc Design And Enhancement Techniques

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Author : Imran Ahmed
language : en
Publisher: Springer Science & Business Media
Release Date : 2010-03-10

Pipelined Adc Design And Enhancement Techniques written by Imran Ahmed and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2010-03-10 with Technology & Engineering categories.

Pipelined ADCs have seen phenomenal improvements in performance over the last few years. As such, when designing a pipelined ADC a clear understanding of the design tradeoffs, and state of the art techniques is required to implement today's high performance low power ADCs.

Generalized Low Voltage Circuit Techniques For Very High Speed Time Interleaved Analog To Digital Converters

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Author : Sai-Weng Sin
language : en
Publisher: Springer Science & Business Media
Release Date : 2010-09-29

Generalized Low Voltage Circuit Techniques For Very High Speed Time Interleaved Analog To Digital Converters written by Sai-Weng Sin and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2010-09-29 with Technology & Engineering categories.

Analog-to-Digital Converters (ADCs) play an important role in most modern signal processing and wireless communication systems where extensive signal manipulation is necessary to be performed by complicated digital signal processing (DSP) circuitry. This trend also creates the possibility of fabricating all functional blocks of a system in a single chip (System On Chip - SoC), with great reductions in cost, chip area and power consumption. However, this tendency places an increasing challenge, in terms of speed, resolution, power consumption, and noise performance, in the design of the front-end ADC which is usually the bottleneck of the whole system, especially under the unavoidable low supply-voltage imposed by technology scaling, as well as the requirement of battery operated portable devices. Generalized Low-Voltage Circuit Techniques for Very High-Speed Time-Interleaved Analog-to-Digital Converters will present new techniques tailored for low-voltage and high-speed Switched-Capacitor (SC) ADC with various design-specific considerations.

Systematic Design For Optimisation Of Pipelined Adcs

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Author : João Goes
language : en
Publisher: Springer Science & Business Media
Release Date : 2006-04-18

Systematic Design For Optimisation Of Pipelined Adcs written by João Goes and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2006-04-18 with Technology & Engineering categories.

This excellent reference proposes and develops new strategies, methodologies and tools for designing low-power and low-area CMOS pipelined A/D converters. The task is tackled by following a scientifically-consistent approach. The book may also be used as a text for advanced reading on the subject.

High Resolution And High Speed Integrated Cmos Ad Converters For Low Power Applications

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Author : Weitao Li
language : en
Publisher: Springer
Release Date : 2017-08-01

High Resolution And High Speed Integrated Cmos Ad Converters For Low Power Applications written by Weitao Li and has been published by Springer this book supported file pdf, txt, epub, kindle and other format this book has been release on 2017-08-01 with Technology & Engineering categories.

This book is a step-by-step tutorial on how to design a low-power, high-resolution (not less than 12 bit), and high-speed (not less than 200 MSps) integrated CMOS analog-to-digital (AD) converter, to respond to the challenge from the rapid growth of IoT. The discussion includes design techniques on both the system level and the circuit block level. In the architecture level, the power-efficient pipelined AD converter, the hybrid AD converter and the time-interleaved AD converter are described. In the circuit block level, the reference voltage buffer, the opamp, the comparator, and the calibration are presented. Readers designing low-power and high-performance AD converters won’t want to miss this invaluable reference. Provides an in-depth introduction to the newest design techniques for the power-efficient, high-resolution (not less than 12 bit), and high-speed (not less than 200 MSps) AD converter; Presents three types of power-efficient architectures of the high-resolution and high-speed AD converter; Discusses the relevant circuit blocks (i.e., the reference voltage buffer, the opamp, and the comparator) in two aspects, relaxing the requirements and improving the performance.

Accuracy Enhancement Techniques In Low Voltage High Speed Pipelined Adc Design

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Author : Jipeng Li
language : en
Publisher:
Release Date : 2003

Accuracy Enhancement Techniques In Low Voltage High Speed Pipelined Adc Design written by Jipeng Li and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2003 with Analog-to-digital converters categories.

Circuit Techniques For Low Voltage And High Speed A D Converters

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Author : Mikko E. Waltari
language : en
Publisher: Springer Science & Business Media
Release Date : 2005-12-30

Circuit Techniques For Low Voltage And High Speed A D Converters written by Mikko E. Waltari and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2005-12-30 with Technology & Engineering categories.

This useful monograph presents a total of seven prototypes: two double-sampled S/H circuits, a time-interleaved ADC, an IF-sampling self-calibrated pipelined ADC, a current steering DAC with a deglitcher, and two pipelined ADCs employing the SO techniques.

Low Power Design Techniques For Analog To Digital Converters In Submicron Cmos

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Author : Tawfiq Musah
language : en
Publisher:
Release Date : 2011

Low Power Design Techniques For Analog To Digital Converters In Submicron Cmos written by Tawfiq Musah and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2011 with Analog-to-digital converters categories.

Advances in process technologies have led to the development of low-power high speed digital signal processing blocks that occupy small areas. These advances are critical in the development of portable electronic devices with small feature size and long battery life. However, the design of analog and mixed-signal building blocks, especially analog-to-digital converters (ADCs), becomes complex and power-inefficient with each advance in process node. This is because of decreased headroom and low intrinsic gain. In this thesis, circuit techniques that enable the design of low-complexity power-efficient ADCs in submicron CMOS are introduced. The techniques include improved correlated level shifting that allow the use of simple low gain amplifiers to realize high performance pipelined and delta-sigma ADCs. Also included is an investigation of the possibility of replacing the power-hungry amplifier in integrators, used in delta-sigma modulators, with low power zero-crossing-based ones. Simulation results of a correlated level shifting pipelined ADC and measurement results of a fabricated prototype of a zero-crossing-based delta-sigma ADC are employed to discuss the effectiveness of the techniques in achieving compact low-power designs.

Reference Free Cmos Pipeline Analog To Digital Converters

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Author : Michael Figueiredo
language : en
Publisher: Springer Science & Business Media
Release Date : 2012-08-24

Reference Free Cmos Pipeline Analog To Digital Converters written by Michael Figueiredo and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2012-08-24 with Technology & Engineering categories.

This book shows that digitally assisted analog to digital converters are not the only way to cope with poor analog performance caused by technology scaling. It describes various analog design techniques that enhance the area and power efficiency without employing any type of digital calibration circuitry. These techniques consist of self-biasing for PVT enhancement, inverter-based design for improved speed/power ratio, gain-of-two obtained by voltage sum instead of charge redistribution, and current-mode reference shifting instead of voltage reference shifting. Together, these techniques allow enhancing the area and power efficiency of the main building blocks of a multiplying digital-to-analog converter (MDAC) based stage, namely, the flash quantizer, the amplifier, and the switched capacitor network of the MDAC. Complementing the theoretical analyses of the various techniques, a power efficient operational transconductance amplifier is implemented and experimentally characterized. Furthermore, a medium-low resolution reference-free high-speed time-interleaved pipeline ADC employing all mentioned design techniques and circuits is presented, implemented and experimentally characterized. This ADC is said to be reference-free because it precludes any reference voltage, therefore saving power and area, as reference circuits are not necessary. Experimental results demonstrate the potential of the techniques which enabled the implementation of area and power efficient circuits.

Low Power High Speed Adcs For Nanometer Cmos Integration

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Author : Zhiheng Cao
language : en
Publisher: Springer Science & Business Media
Release Date : 2008-07-15

Low Power High Speed Adcs For Nanometer Cmos Integration written by Zhiheng Cao and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2008-07-15 with Technology & Engineering categories.

Low-Power High-Speed ADCs for Nanometer CMOS Integration is about the design and implementation of ADC in nanometer CMOS processes that achieve lower power consumption for a given speed and resolution than previous designs, through architectural and circuit innovations that take advantage of unique features of nanometer CMOS processes. A phase lock loop (PLL) clock multiplier has also been designed using new circuit techniques and successfully tested. 1) A 1.2V, 52mW, 210MS/s 10-bit two-step ADC in 130nm CMOS occupying 0.38mm2. Using offset canceling comparators and capacitor networks implemented with small value interconnect capacitors to replace resistor ladder/multiplexer in conventional sub-ranging ADCs, it achieves 74dB SFDR for 10MHz and 71dB SFDR for 100MHz input. 2) A 32mW, 1.25GS/s 6-bit ADC with 2.5GHz internal clock in 130nm CMOS. A new type of architecture that combines flash and SAR enables the lowest power consumption, 6-bit >1GS/s ADC reported to date. This design can be a drop-in replacement for existing flash ADCs since it does require any post-processing or calibration step and has the same latency as flash. 3) A 0.4ps-rms-jitter (integrated from 3kHz to 300MHz offset for >2.5GHz) 1-3GHz tunable, phase-noise programmable clock-multiplier PLL for generating sampling clock to the SAR ADC. A new loop filter structure enables phase error preamplification to lower PLL in-band noise without increasing loop filter capacitor size.