On Chip Digital Background Calibration Of Pipelined Analog To Digital Converters Using Digital Assistance To Support Nonlinear Residue Amplification

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On Chip Digital Background Calibration Of Pipelined Analog To Digital Converters Using Digital Assistance To Support Nonlinear Residue Amplification

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Author : Thomas Liechti
language : en
Publisher:
Release Date : 2012

On Chip Digital Background Calibration Of Pipelined Analog To Digital Converters Using Digital Assistance To Support Nonlinear Residue Amplification written by Thomas Liechti and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2012 with categories.

Pipelined Analog To Digital Conversion Using Class Ab Amplifiers

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Author : Kyung Ryun Kim
language : en
Publisher: Stanford University
Release Date : 2010

Pipelined Analog To Digital Conversion Using Class Ab Amplifiers written by Kyung Ryun Kim and has been published by Stanford University this book supported file pdf, txt, epub, kindle and other format this book has been release on 2010 with categories.

In high-performance pipelined analog-to-digital converters (ADCs), the residue amplifiers dissipate the majority of the overall converter power. Therefore, finding alternatives to the relatively inefficient, conventional class-A circuit realization is an active area of research. One option for improvement is to employ class-AB amplifiers, which can, in principle, provide large drive currents on demand and improve the efficiency of residue amplification. Unfortunately, due to the simultaneous demand for high speed and high gain in pipelined ADCs, the improvements seen in class-AB designs have so far been limited. This dissertation presents the design of an efficient class-AB amplification scheme based on a pseudo-differential, single-stage and cascode-free architecture. Nonlinear errors due to finite DC gain are addressed using a deterministic digital background calibration that measures the circuit imperfections in time intervals between normal conversion cycles of the ADC. As a proof of concept, a 12-bit 30-MS/s pipelined ADC was realized using class-AB amplifiers with the proposed digital calibration. The prototype ADC occupies an active area of 0.36 mm2 in 90-nm CMOS. It dissipates 2.95 mW from a 1.2-V supply and achieves an SNDR of 64.5 dB for inputs near the Nyquist frequency. The corresponding figure of merit is 72 fJ/conversion-step.

Pipelined Analog To Digital Conversion Using Class Ab Amplifiers

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Author : Kyung Ryun Kim
language : en
Publisher:
Release Date : 2010

Pipelined Analog To Digital Conversion Using Class Ab Amplifiers written by Kyung Ryun Kim and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2010 with categories.

In high-performance pipelined analog-to-digital converters (ADCs), the residue amplifiers dissipate the majority of the overall converter power. Therefore, finding alternatives to the relatively inefficient, conventional class-A circuit realization is an active area of research. One option for improvement is to employ class-AB amplifiers, which can, in principle, provide large drive currents on demand and improve the efficiency of residue amplification. Unfortunately, due to the simultaneous demand for high speed and high gain in pipelined ADCs, the improvements seen in class-AB designs have so far been limited. This dissertation presents the design of an efficient class-AB amplification scheme based on a pseudo-differential, single-stage and cascode-free architecture. Nonlinear errors due to finite DC gain are addressed using a deterministic digital background calibration that measures the circuit imperfections in time intervals between normal conversion cycles of the ADC. As a proof of concept, a 12-bit 30-MS/s pipelined ADC was realized using class-AB amplifiers with the proposed digital calibration. The prototype ADC occupies an active area of 0.36 mm2 in 90-nm CMOS. It dissipates 2.95 mW from a 1.2-V supply and achieves an SNDR of 64.5 dB for inputs near the Nyquist frequency. The corresponding figure of merit is 72 fJ/conversion-step.

Background Digital Calibration For Interstage Gain Errors And Memory Effects In Pipelined Analog To Digital Converters

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Author : John Patrick Keane
language : en
Publisher:
Release Date : 2004

Background Digital Calibration For Interstage Gain Errors And Memory Effects In Pipelined Analog To Digital Converters written by John Patrick Keane and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2004 with categories.

Nested Digital Background Calibration Of Pipelined Analog To Digital Converters

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Author : Xiaoyue Wang
language : en
Publisher:
Release Date : 2003

Nested Digital Background Calibration Of Pipelined Analog To Digital Converters written by Xiaoyue Wang and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2003 with categories.

Reference Free Cmos Pipeline Analog To Digital Converters

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Author : Michael Figueiredo
language : en
Publisher: Springer Science & Business Media
Release Date : 2012-08-24

Reference Free Cmos Pipeline Analog To Digital Converters written by Michael Figueiredo and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2012-08-24 with Technology & Engineering categories.

This book shows that digitally assisted analog to digital converters are not the only way to cope with poor analog performance caused by technology scaling. It describes various analog design techniques that enhance the area and power efficiency without employing any type of digital calibration circuitry. These techniques consist of self-biasing for PVT enhancement, inverter-based design for improved speed/power ratio, gain-of-two obtained by voltage sum instead of charge redistribution, and current-mode reference shifting instead of voltage reference shifting. Together, these techniques allow enhancing the area and power efficiency of the main building blocks of a multiplying digital-to-analog converter (MDAC) based stage, namely, the flash quantizer, the amplifier, and the switched capacitor network of the MDAC. Complementing the theoretical analyses of the various techniques, a power efficient operational transconductance amplifier is implemented and experimentally characterized. Furthermore, a medium-low resolution reference-free high-speed time-interleaved pipeline ADC employing all mentioned design techniques and circuits is presented, implemented and experimentally characterized. This ADC is said to be reference-free because it precludes any reference voltage, therefore saving power and area, as reference circuits are not necessary. Experimental results demonstrate the potential of the techniques which enabled the implementation of area and power efficient circuits.

Analog Background Calibration Of Parallel Pipelined Analog To Digital Converters

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Author : Kenneth Colin Dyer
language : en
Publisher:
Release Date : 1998

Analog Background Calibration Of Parallel Pipelined Analog To Digital Converters written by Kenneth Colin Dyer and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 1998 with Analog-to-digital converters categories.

Background Analog And Digital Calibration Techniques For Pipelined Adc S

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Author : Sudipta Sarkar
language : en
Publisher:
Release Date : 2017

Background Analog And Digital Calibration Techniques For Pipelined Adc S written by Sudipta Sarkar and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2017 with Comparator circuits categories.

A digital background calibration technique to treat capacitor mismatch, residue gain error and nonlinearity in a pipelined analog-to-digital converter (ADC) based on the split-ADC architecture (J. McNeill et al., “Split ADC architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC,” IEEE J. of Solid-State Circuits, vol. 40, pp. 2437-2445, Dec. 2005) is reported. Although multiple works have been reported before on the split-calibration of pipelined analog-to-digital converters, none of them is comprehensive, i.e., capacitor mismatch, residue gain error and nonlinearity are never treated in one work at the same time. We, for the first time, recognize the multistage pipelined ADC with residue non-linearity calibration as a Nonlinear Least Squares problem. Behavioral simulation results demonstrate the efficacy of the technique, in which the signal-to-noise-and-distortion ratio (SNDR) and spurious-free-dynamic-range (SFDR) performance of a 15-bit split-pipelined ADC are improved from 42 dB and 50 dB to 88 dB and 102 dB on average, respectively. Secondly, an 8b, 1.3/1.39GS/s, 7/8.1mW two-step ADC is presented that introduces a single reference comparator based background comparator offset calibration technique. This work employs a dual-residue based inter-stage redundancy scheme to relax residue amplifier specifications (and enable high-speed operation at 0.85V supply) in a two-step ADC. Comparator offset calibration is implemented through body biasing with an area-efficient 8b offset calibration DAC. A prototype in 28nm Complementary Metal Oxide Semiconductor (CMOS) achieves 6.8 effective number of bits (ENOB) and 50fJ/c-s at DC and 6.3 ENOB and 68fJ/c-s at Nyquist, at a sample rate of 1.3GS/s. The measured SNDR/SFDR improve from 29.2/40.7dB to 42.6/57.7dB after calibration. The active area is 0.05mm2.

Nested Digital Background Calibration Of A 12 Bit Pipelined Adc Without An Input Sha

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Author : Haoyue Wang
language : en
Publisher:
Release Date : 2008

Nested Digital Background Calibration Of A 12 Bit Pipelined Adc Without An Input Sha written by Haoyue Wang and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2008 with categories.

Noise Speed And Power Tradeoffs In Pipelined Analog To Digital Converters

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Author : David William Cline
language : en
Publisher:
Release Date : 1995

Noise Speed And Power Tradeoffs In Pipelined Analog To Digital Converters written by David William Cline and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 1995 with categories.