Wafer Scale Integration
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Wafer Scale Integration
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Author : Earl E. Swartzlander Jr.
language : en
Publisher: Springer Science & Business Media
Release Date : 2012-12-06
Wafer Scale Integration written by Earl E. Swartzlander Jr. and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2012-12-06 with Technology & Engineering categories.
Wafer Scale Integration (WSI) is the culmination of the quest for larger integrated circuits. In VLSI chips are developed by fabricating a wafer with hundreds of identical circuits, testing the circuits, dicing the wafer, and packaging the good dice. In contrast in WSI, a wafer is fabricated with several types of circuits (generally referred to as cells), with multiple instances of each cell type, the cells are tested, and good cells are interconnected to realize a system on the wafer. Since most signal lines stay on the wafer, stray capacitance is low, so that high speeds are achieved with low power consumption. For the same technology a WSI implementation may be a factor of five faster, dissipate a factor of ten less power, and require one hundredth to one thousandth the volume. Successful development of WSI involves many overlapping disciplines, ranging from architecture to test design to fabrication (including laser linking and cutting, multiple levels of interconnection, and packaging). This book concentrates on the areas that are unique to WSI and that are as a result not well covered by any of the many books on VLSI design. A unique aspect of WSI is that the finished circuits are so large that there will be defects in some portions of the circuit. Accordingly much attention must be devoted to designing architectures that facilitate fault detection and reconfiguration to of WSI include fabrication circumvent the faults. Other unique aspects technology and packaging.
Wafer Scale Integration
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Author : C. R. Jesshope
language : en
Publisher: CRC Press
Release Date : 1986
Wafer Scale Integration written by C. R. Jesshope and has been published by CRC Press this book supported file pdf, txt, epub, kindle and other format this book has been release on 1986 with Art categories.
This book, the first to deal wholly with the topic of wafer scale integration, is the edited proceedings of a workshop held at the University of Southampton in July 1985. As the first international meeting held on this subject it attracted many participants from Europe and the United States. The meeting was particularly timely as there has recently been a renewed interest in research and commercial exploitation of wafer scale integration. The papers presented in the book cover the whole range of topics important in wafer scale integration, beginning with a critical review of fault-tolerant chips and wafer scale integration. Sections on general problems and interconnection strategies follow. There are then six papaers on architectures and four on restructurable very large scale integration. The book concludes with three reviews of different aspects of testability.
Wafer Level 3 D Ics Process Technology
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Author : Chuan Seng Tan
language : en
Publisher: Springer Science & Business Media
Release Date : 2009-06-29
Wafer Level 3 D Ics Process Technology written by Chuan Seng Tan and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2009-06-29 with Technology & Engineering categories.
This book focuses on foundry-based process technology that enables the fabrication of 3-D ICs. The core of the book discusses the technology platform for pre-packaging wafer lever 3-D ICs. However, this book does not include a detailed discussion of 3-D ICs design and 3-D packaging. This is an edited book based on chapters contributed by various experts in the field of wafer-level 3-D ICs process technology. They are from academia, research labs and industry.
Wafer Level Integrated Systems
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Author : Stuart K. Tewksbury
language : en
Publisher: Springer Science & Business Media
Release Date : 2012-12-06
Wafer Level Integrated Systems written by Stuart K. Tewksbury and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2012-12-06 with Technology & Engineering categories.
From the perspective of complex systems, conventional Ie's can be regarded as "discrete" devices interconnected according to system design objectives imposed at the circuit board level and higher levels in the system implementation hierarchy. However, silicon monolithic circuits have progressed to such complex functions that a transition from a philosophy of integrated circuits (Ie's) to one of integrated sys tems is necessary. Wafer-scale integration has played an important role over the past few years in highlighting the system level issues which will most significantly impact the implementation of complex monolithic systems and system components. Rather than being a revolutionary approach, wafer-scale integration will evolve naturally from VLSI as defect avoidance, fault tolerance and testing are introduced into VLSI circuits. Successful introduction of defect avoidance, for example, relaxes limits imposed by yield and cost on Ie dimensions, allowing the monolithic circuit's area to be chosen according to the natural partitioning of a system into individual functions rather than imposing area limits due to defect densities. The term "wafer level" is perhaps more appropriate than "wafer-scale". A "wafer-level" monolithic system component may have dimensions ranging from conventional yield-limited Ie dimensions to full wafer dimensions. In this sense, "wafer-scale" merely represents the obvious upper practical limit imposed by wafer sizes on the area of monolithic circuits. The transition to monolithic, wafer-level integrated systems will require a mapping of the full range of system design issues onto the design of monolithic circuit.
Wafer Scale Integration Ii
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Author : R. M. Lea
language : en
Publisher: North Holland
Release Date : 1988
Wafer Scale Integration Ii written by R. M. Lea and has been published by North Holland this book supported file pdf, txt, epub, kindle and other format this book has been release on 1988 with Computers categories.
Wafer Scale Integration Iii
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Author : Mariagiovanna Sami
language : en
Publisher: North Holland
Release Date : 1990
Wafer Scale Integration Iii written by Mariagiovanna Sami and has been published by North Holland this book supported file pdf, txt, epub, kindle and other format this book has been release on 1990 with Technology & Engineering categories.
The purpose of this book is to give an up-to-date presentation of architectures and technologies for wafer-scale integration. As such, it is an overview of the work of the leading research centers active in this area, and an outline of expected evolution and progress in the subject. New technological solutions are envisioned; while the use of optical technologies for interconnections promises to overcome one of the main restrictions to architectures on a wafer, the extension of quick-prototyping solutions to the wafer dimension allows the introduction of wafer-scale systems in educational environments as well as in applications where a quick result and limited production would make traditional silicon solutions unacceptable. Regarding architectures and their applications, three different lines of approach can be identified. Evolutive solutions are proposed, mainly concerning array architectures and restructuring techniques. Innovative architectures are presented, several papers dealing with neural nets. There are also architectures designed not just for experimental reasons but for industrial production. Overall, non-numerical applications predominate.
Soft Configurable Wafer Scale Integration
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Author : M. G. Blatt
language : en
Publisher:
Release Date : 1990
Soft Configurable Wafer Scale Integration written by M. G. Blatt and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 1990 with Fault-tolerant computing categories.
The redundancy models constrain wafer yield by system requirements such as the minimum number of working circuit units, and whether these working units are distributed evenly around the wafer. Choice of redundancy model significantly affects the resulting wafer yield."
Wafer Level Chip Scale Packaging
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Author : Shichun Qu
language : en
Publisher: Springer
Release Date : 2014-09-10
Wafer Level Chip Scale Packaging written by Shichun Qu and has been published by Springer this book supported file pdf, txt, epub, kindle and other format this book has been release on 2014-09-10 with Technology & Engineering categories.
Analog and Power Wafer Level Chip Scale Packaging presents a state-of-art and in-depth overview in analog and power WLCSP design, material characterization, reliability and modeling. Recent advances in analog and power electronic WLCSP packaging are presented based on the development of analog technology and power device integration. The book covers in detail how advances in semiconductor content, analog and power advanced WLCSP design, assembly, materials and reliability have co-enabled significant advances in fan-in and fan-out with redistributed layer (RDL) of analog and power device capability during recent years. Since the analog and power electronic wafer level packaging is different from regular digital and memory IC package, this book will systematically introduce the typical analog and power electronic wafer level packaging design, assembly process, materials, reliability and failure analysis, and material selection. Along with new analog and power WLCSP development, the role of modeling is a key to assure successful package design. An overview of the analog and power WLCSP modeling and typical thermal, electrical and stress modeling methodologies is also presented in the book.
Wafer Scale Integration
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Author : Glenn Chapman
language : en
Publisher:
Release Date : 1994
Wafer Scale Integration written by Glenn Chapman and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 1994 with Integrated circuits categories.
Seventh Annual Ieee International Conference On Wafer Scale Integration San Francisco California Usa
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Author : Glenn Chapman
language : en
Publisher: Institute of Electrical & Electronics Engineers(IEEE)
Release Date : 1995
Seventh Annual Ieee International Conference On Wafer Scale Integration San Francisco California Usa written by Glenn Chapman and has been published by Institute of Electrical & Electronics Engineers(IEEE) this book supported file pdf, txt, epub, kindle and other format this book has been release on 1995 with Technology & Engineering categories.