Digital Calibration Algorithms For Nyquist Rate Analog To Digital Converters
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Digital Calibration Algorithms For Nyquist Rate Analog To Digital Converters
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Author : Anup Savla
language : en
Publisher:
Release Date : 2004
Digital Calibration Algorithms For Nyquist Rate Analog To Digital Converters written by Anup Savla and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2004 with Analog-to-digital converters categories.
Abstract: Continuous scaling down of CMOS device sizes and an accompanied increase in device switching speeds prompts the design of mixed-signal systems with increasingly complex digital signal processing and control algorithms accompanied by simpler analog circuitry. Analog to digital converter (ADC) is an essential mixed-signal component of modern receivers, where signals sensed from the source are converted to digital for further signal processing on them. In this dissertation, calibration techniques are presented which allow ADCs to be designed with large inherent gain and offset errors. The concept of arbitrary radix multistep conversion is presented, along with algorithms that enable reduced radix conversion with digital correction in pipelined or algorithmic ADCs. Calibration techniques that account for linear and nonlinear gain error are presented and adapted to the popular 1.5 bit/stage pipeline architecture. Calibration is performed purely with digital post-processing on ADC output bits, with no changes occurring in the analog hardware. In this dissertation a WCDMA/WLAN receiver architecture is presented and specifications are derived for all its components. Concept of reconfigurable ADC design is presented, which allows speed and power consumption optimization. Reduced radix digital correction, linear and nonlinear calibration and background-calibrating queues are presented and combined in two behavioral models. The reconfigurable ADC was fabricated in AMI0.5u 3V CMOS process, and achieved 55dB dynamic range at 45MS/s, consuming 51mW power. The reconfigured calibrated ADC was simulated in TSMC 0.18u 1.8V CMOS process, and achieved 63dB dynamic range at 25MS/s, consuming 3.6mW power. Measurements of the capture card showed a 1.6bit improvement in resolution with the use of calibration algorithms.
Digitally Assisted Techniques For Nyquist Rate Analog To Digital Converters
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Author : Rabeeh Majidi
language : en
Publisher:
Release Date : 2015
Digitally Assisted Techniques For Nyquist Rate Analog To Digital Converters written by Rabeeh Majidi and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2015 with categories.
Abstract: With the advance of technology and rapid growth of digital systems, low power high speed analog-to- digital converters with great accuracy are in demand. To achieve high effective number of bits Analog-to-Digital Converter (ADC) calibration as a time consuming process is a potential bottleneck for designs. This dissertation presentsa fully digital background calibration algorithm for a 7- bit redundant flash ADC using split structure and look-up table based correction. Redundant comparators are used in the flash ADC design of this work in order to tolerate large offset voltages while minimizing signal input capacitance. The split ADC structure helps by eliminating the unknown input signal from the calibration path. The flash ADC has been designed in 180nm IBM CMOS technology and fabricated through MOSIS. This work was supported by Analog Devices, Wilmington, MA. While much research on ADC design has concentrated on increasing resolution and sample rate, there are many applications (e.g. biomedical devices and sensor networks) that do not require high performance but do require low power energy efficient ADCs. This dissertation also explores on design of a low quiescent current 100k Sps Successive Approximation (SAR) ADC that has been used as an error detection ADC for an automotive application in 350nm CD (CMOS-DMOS) technology. This work was supported by ON Semiconductor Corp, East Greenwich, RI.
Digital Background Calibration Of Analog To Digital Converters Using A Calibration Queue
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Author : Ozan Ersan Erdoğan
language : en
Publisher:
Release Date : 1999
Digital Background Calibration Of Analog To Digital Converters Using A Calibration Queue written by Ozan Ersan Erdoğan and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 1999 with categories.
Digital Calibration Of Double Sampled Time Interleaved Analog To Digital Converters
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Author : Chi Ho Law
language : en
Publisher:
Release Date : 2009
Digital Calibration Of Double Sampled Time Interleaved Analog To Digital Converters written by Chi Ho Law and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2009 with categories.
Signal Reconstruction Algorithms For Time Interleaved Adcs
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Author : Anu Kalidas Muralidharan Pillai
language : en
Publisher: Linköping University Electronic Press
Release Date : 2015-05-22
Signal Reconstruction Algorithms For Time Interleaved Adcs written by Anu Kalidas Muralidharan Pillai and has been published by Linköping University Electronic Press this book supported file pdf, txt, epub, kindle and other format this book has been release on 2015-05-22 with Algorithms categories.
An analog-to-digital converter (ADC) is a key component in many electronic systems. It is used to convert analog signals to the equivalent digital form. The conversion involves sampling which is the process of converting a continuous-time signal to a sequence of discrete-time samples, and quantization in which each sampled value is represented using a finite number of bits. The sampling rate and the effective resolution (number of bits) are two key ADC performance metrics. Today, ADCs form a major bottleneck in many applications like communication systems since it is difficult to simultaneously achieve high sampling rate and high resolution. Among the various ADC architectures, the time-interleaved analog-to-digital converter (TI-ADC) has emerged as a popular choice for achieving very high sampling rates and resolutions. At the principle level, by interleaving the outputs of M identical channel ADCs, a TI-ADC could achieve the same resolution as that of a channel ADC but with M times higher bandwidth. However, in practice, mismatches between the channel ADCs result in a nonuniformly sampled signal at the output of a TI-ADC which reduces the achievable resolution. Often, in TIADC implementations, digital reconstructors are used to recover the uniform-grid samples from the nonuniformly sampled signal at the output of the TI-ADC. Since such reconstructors operate at the TI-ADC output rate, reducing the number of computations required per corrected output sample helps to reduce the power consumed by the TI-ADC. Also, as the mismatch parameters change occasionally, the reconstructor should support online reconfiguration with minimal or no redesign. Further, it is advantageous to have reconstruction schemes that require fewer coefficient updates during reconfiguration. In this thesis, we focus on reducing the design and implementation complexities of nonrecursive finite-length impulse response (FIR) reconstructors. We propose efficient reconstruction schemes for three classes of nonuniformly sampled signals that can occur at the output of TI-ADCs. Firstly, we consider a class of nonuniformly sampled signals that occur as a result of static timing mismatch errors or due to channel mismatches in TI-ADCs. For this type of nonuniformly sampled signals, we propose three reconstructors which utilize a two-rate approach to derive the corresponding single-rate structure. The two-rate based reconstructors move part of the complexity to a symmetric filter and also simplifies the reconstruction problem. The complexity reduction stems from the fact that half of the impulse response coefficients of the symmetric filter are equal to zero and that, compared to the original reconstruction problem, the simplified problem requires only a simpler reconstructor. Next, we consider the class of nonuniformly sampled signals that occur when a TI-ADC is used for sub-Nyquist cyclic nonuniform sampling (CNUS) of sparse multi-band signals. Sub-Nyquist sampling utilizes the sparsities in the analog signal to sample the signal at a lower rate. However, the reduced sampling rate comes at the cost of additional digital signal processing that is needed to reconstruct the uniform-grid sequence from the sub-Nyquist sampled sequence obtained via CNUS. The existing reconstruction scheme is computationally intensive and time consuming and offsets the gains obtained from the reduced sampling rate. Also, in applications where the band locations of the sparse multi-band signal can change from time to time, the reconstructor should support online reconfigurability. Here, we propose a reconstruction scheme that reduces the computational complexity of the reconstructor and at the same time, simplifies the online reconfigurability of the reconstructor. Finally, we consider a class of nonuniformly sampled signals which occur at the output of TI-ADCs that use some of the input sampling instants for sampling a known calibration signal. The samples corresponding to the calibration signal are used for estimating the channel mismatch parameters. In such TI-ADCs, nonuniform sampling is due to the mismatches between the channel ADCs and due to the missing input samples corresponding to the sampling instants reserved for the calibration signal. We propose three reconstruction schemes for such nonuniformly sampled signals and show using design examples that, compared to a previous solution, the proposed schemes require substantially lower computational complexity.
Calibration Techniques In Nyquist A D Converters
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Author : Hendrik van der Ploeg
language : en
Publisher: Springer Science & Business Media
Release Date : 2006-09-13
Calibration Techniques In Nyquist A D Converters written by Hendrik van der Ploeg and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2006-09-13 with Technology & Engineering categories.
This book analyses different A/D-converter architectures with an emphasis on the maximum achievable power efficiency. It also provides an accessible overview of the state-of-the art in calibration techniques for Nyquist A/D converters. The calibration techniques presented are applicable to other analog-to-digital systems, such as those applied in integrated receivers. They allow implementation without introducing a speed or power penalty.
Pipelined Analog To Digital Conversion Using Class Ab Amplifiers
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Author : Kyung Ryun Kim
language : en
Publisher: Stanford University
Release Date : 2010
Pipelined Analog To Digital Conversion Using Class Ab Amplifiers written by Kyung Ryun Kim and has been published by Stanford University this book supported file pdf, txt, epub, kindle and other format this book has been release on 2010 with categories.
In high-performance pipelined analog-to-digital converters (ADCs), the residue amplifiers dissipate the majority of the overall converter power. Therefore, finding alternatives to the relatively inefficient, conventional class-A circuit realization is an active area of research. One option for improvement is to employ class-AB amplifiers, which can, in principle, provide large drive currents on demand and improve the efficiency of residue amplification. Unfortunately, due to the simultaneous demand for high speed and high gain in pipelined ADCs, the improvements seen in class-AB designs have so far been limited. This dissertation presents the design of an efficient class-AB amplification scheme based on a pseudo-differential, single-stage and cascode-free architecture. Nonlinear errors due to finite DC gain are addressed using a deterministic digital background calibration that measures the circuit imperfections in time intervals between normal conversion cycles of the ADC. As a proof of concept, a 12-bit 30-MS/s pipelined ADC was realized using class-AB amplifiers with the proposed digital calibration. The prototype ADC occupies an active area of 0.36 mm2 in 90-nm CMOS. It dissipates 2.95 mW from a 1.2-V supply and achieves an SNDR of 64.5 dB for inputs near the Nyquist frequency. The corresponding figure of merit is 72 fJ/conversion-step.
Digital Background Calibration Of Time Interleaved Analog To Digital Converters
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Author : Shafiq M. Jamal
language : en
Publisher:
Release Date : 2001
Digital Background Calibration Of Time Interleaved Analog To Digital Converters written by Shafiq M. Jamal and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2001 with Analog-to-digital converters categories.
Monolithic Nyquist Rate Analog To Digital Converter With Digital Calibration
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Author : Yang Wu
language : en
Publisher:
Release Date : 2002
Monolithic Nyquist Rate Analog To Digital Converter With Digital Calibration written by Yang Wu and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2002 with categories.
"The design details of pipeline ADC is also discussed in this work. Quantitative analyses have been provided in determining design parameters in various subsystems. The analyses ensure that a 10-bit resolution is achieved for the pipeline ADC. Both Flash ADC and pipeline ADC were implemented in a 0.25 mum and 0.18 mum CMOS process respectively, and results demonstrating their successful operation are presented." --
Incremental Data Converters For Sensor Interfaces
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Author : Chia-Hung Chen
language : en
Publisher: John Wiley & Sons
Release Date : 2023-12-19
Incremental Data Converters For Sensor Interfaces written by Chia-Hung Chen and has been published by John Wiley & Sons this book supported file pdf, txt, epub, kindle and other format this book has been release on 2023-12-19 with Technology & Engineering categories.
Comprehensive resource discussing operating principles, available architectures, and design of micropower incremental analog-to-digital converters (IADCs) Incremental Data Converters for Sensor Interfaces describes the motivation for using incremental analog-to-digital converters (IADCs), including the theoretical foundations of their operation, the trade-offs in their use, and the practical issues in the circuit analysis and design of IADCs. The text covers core foundational knowledge such as the key algorithms used, circuits for single-stage and multi-stage IADCs, the design of the digital post filters for single- and multi-stage IADCs, IADC applications in measurement and instrumentation, medicine, imagers, and IoT, and comparison of delta-sigma (D-S) and incremental ADCs (IADCs) in terms of accuracy, latency, and multiplexed operation. To aid in reader comprehension and serve as an excellent classroom learning resource, Incremental Data Converters for Sensor Interfaces includes in-text problems and homework for graduate studies, along with helpful computer codes in MATLAB and Simulink. Additional topics covered in Incremental Data Converters for Sensor Interfaces include: Sensors and sensor interfaces, mixed-mode (analog–digital) communication and consumer signal chains, and ADC algorithms Quantization errors vs. quantization noise, and performance parameters and figures of merit, including resolution, linearity, accuracy, bandwidth, latency, and power dissipation Nyquist-rate and oversampling data converters, noise-shaping ADCs, and basic architectures for IADCs, including single- and multi-stage designs and discrete vs. continuous-time operation Loop filter design, D/A converter design, dynamic element matching and digital calibration, and quantizer design With comprehensive coverage of foundational knowledge surrounding the subject, various real-world examples, and helpful learning aids, Incremental Data Converters for Sensor Interfaces is an essential resource for graduate students in electronics programs, along with industrial circuit design professionals.