Iddq Testing Of Vlsi Circuits
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Introduction To Iddq Testing
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Author : S. Chakravarty
language : en
Publisher: Springer Science & Business Media
Release Date : 2012-12-06
Introduction To Iddq Testing written by S. Chakravarty and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2012-12-06 with Technology & Engineering categories.
Testing techniques for VLSI circuits are undergoing many exciting changes. The predominant method for testing digital circuits consists of applying a set of input stimuli to the IC and monitoring the logic levels at primary outputs. If, for one or more inputs, there is a discrepancy between the observed output and the expected output then the IC is declared to be defective. A new approach to testing digital circuits, which has come to be known as IDDQ testing, has been actively researched for the last fifteen years. In IDDQ testing, the steady state supply current, rather than the logic levels at the primary outputs, is monitored. Years of research suggests that IDDQ testing can significantly improve the quality and reliability of fabricated circuits. This has prompted many semiconductor manufacturers to adopt this testing technique, among them Philips Semiconductors, Ford Microelectronics, Intel, Texas Instruments, LSI Logic, Hewlett-Packard, SUN microsystems, Alcatel, and SGS Thomson. This increase in the use of IDDQ testing should be of interest to three groups of individuals associated with the IC business: Product Managers and Test Engineers, CAD Tool Vendors and Circuit Designers. Introduction to IDDQ Testing is designed to educate this community. The authors have summarized in one volume the main findings of more than fifteen years of research in this area.
Iddq Testing Of Vlsi Circuits
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Author : Ravi K. Gulati
language : en
Publisher: Springer Science & Business Media
Release Date : 2012-12-06
Iddq Testing Of Vlsi Circuits written by Ravi K. Gulati and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2012-12-06 with Computers categories.
Power supply current monitoring to detect CMOS IC defects during production testing quietly laid down its roots in the mid-1970s. Both Sandia Labs and RCA in the United States and Philips Labs in the Netherlands practiced this procedure on their CMOS ICs. At that time, this practice stemmed simply from an intuitive sense that CMOS ICs showing abnormal quiescent power supply current (IDDQ) contained defects. Later, this intuition was supported by data and analysis in the 1980s by Levi (RACD, Malaiya and Su (SUNY-Binghamton), Soden and Hawkins (Sandia Labs and the University of New Mexico), Jacomino and co-workers (Laboratoire d'Automatique de Grenoble), and Maly and co-workers (Carnegie Mellon University). Interest in IDDQ testing has advanced beyond the data reported in the 1980s and is now focused on applications and evaluations involving larger volumes of ICs that improve quality beyond what can be achieved by previous conventional means. In the conventional style of testing one attempts to propagate the logic states of the suspended nodes to primary outputs. This is done for all or most nodes of the circuit. For sequential circuits, in particular, the complexity of finding suitable tests is very high. In comparison, the IDDQ test does not observe the logic states, but measures the integrated current that leaks through all gates. In other words, it is like measuring a patient's temperature to determine the state of health. Despite perceived advantages, during the years that followed its initial announcements, skepticism about the practicality of IDDQ testing prevailed. The idea, however, provided a great opportunity to researchers. New results on test generation, fault simulation, design for testability, built-in self-test, and diagnosis for this style of testing have since been reported. After a decade of research, we are definitely closer to practice.
Iddq Testing Of Vlsi Circuits
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Author : Chuck Hawkins
language : en
Publisher:
Release Date : 1995
Iddq Testing Of Vlsi Circuits written by Chuck Hawkins and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 1995 with categories.
Essentials Of Electronic Testing For Digital Memory And Mixed Signal Vlsi Circuits
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Author : M. Bushnell
language : en
Publisher: Springer Science & Business Media
Release Date : 2006-04-11
Essentials Of Electronic Testing For Digital Memory And Mixed Signal Vlsi Circuits written by M. Bushnell and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2006-04-11 with Technology & Engineering categories.
The modern electronic testing has a forty year history. Test professionals hold some fairly large conferences and numerous workshops, have a journal, and there are over one hundred books on testing. Still, a full course on testing is offered only at a few universities, mostly by professors who have a research interest in this area. Apparently, most professors would not have taken a course on electronic testing when they were students. Other than the computer engineering curriculum being too crowded, the major reason cited for the absence of a course on electronic testing is the lack of a suitable textbook. For VLSI the foundation was provided by semiconductor device techn- ogy, circuit design, and electronic testing. In a computer engineering curriculum, therefore, it is necessary that foundations should be taught before applications. The field of VLSI has expanded to systems-on-a-chip, which include digital, memory, and mixed-signalsubsystems. To our knowledge this is the first textbook to cover all three types of electronic circuits. We have written this textbook for an undergraduate “foundations” course on electronic testing. Obviously, it is too voluminous for a one-semester course and a teacher will have to select from the topics. We did not restrict such freedom because the selection may depend upon the individual expertise and interests. Besides, there is merit in having a larger book that will retain its usefulness for the owner even after the completion of the course. With equal tenacity, we address the needs of three other groups of readers.
Current Comparator Design For Iddq Testing In Vlsi Circuits
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Author : Umesh Mehta
language : en
Publisher:
Release Date : 1996
Current Comparator Design For Iddq Testing In Vlsi Circuits written by Umesh Mehta and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 1996 with Iddq testing categories.
Iddq Testing For Cmos Vlsi
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Author : Rochit Rajsuman
language : en
Publisher: Artech House Publishers
Release Date : 1995
Iddq Testing For Cmos Vlsi written by Rochit Rajsuman and has been published by Artech House Publishers this book supported file pdf, txt, epub, kindle and other format this book has been release on 1995 with Technology & Engineering categories.
This book discusses in detail the correlation between physical defects and logic faults, and shows you how Iddq testing locates these defects. The book provides planning guidelines and optimization methods and is illustrated with numerous examples ranging from simple circuits to extensive case studies.
Defect Oriented Testing For Nano Metric Cmos Vlsi Circuits
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Author : Manoj Sachdev
language : en
Publisher: Springer Science & Business Media
Release Date : 2007-06-04
Defect Oriented Testing For Nano Metric Cmos Vlsi Circuits written by Manoj Sachdev and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2007-06-04 with Technology & Engineering categories.
The 2nd edition of defect oriented testing has been extensively updated. New chapters on Functional, Parametric Defect Models and Inductive fault Analysis and Yield Engineering have been added to provide a link between defect sources and yield. The chapter on RAM testing has been updated with focus on parametric and SRAM stability testing. Similarly, newer material has been incorporated in digital fault modeling and analog testing chapters. The strength of Defect Oriented Testing for nano-Metric CMOS VLSIs lies in its industrial relevance.
Delay Fault Testing For Vlsi Circuits
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Author : Angela Krstic
language : en
Publisher: Springer Science & Business Media
Release Date : 2012-12-06
Delay Fault Testing For Vlsi Circuits written by Angela Krstic and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2012-12-06 with Technology & Engineering categories.
In the early days of digital design, we were concerned with the logical correctness of circuits. We knew that if we slowed down the clock signal sufficiently, the circuit would function correctly. With improvements in the semiconductor process technology, our expectations on speed have soared. A frequently asked question in the last decade has been how fast can the clock run. This puts significant demands on timing analysis and delay testing. Fueled by the above events, a tremendous growth has occurred in the research on delay testing. Recent work includes fault models, algorithms for test generation and fault simulation, and methods for design and synthesis for testability. The authors of this book, Angela Krstic and Tim Cheng, have personally contributed to this research. Now they do an even greater service to the profession by collecting the work of a large number of researchers. In addition to expounding such a great deal of information, they have delivered it with utmost clarity. To further the reader's understanding many key concepts are illustrated by simple examples. The basic ideas of delay testing have reached a level of maturity that makes them suitable for practice. In that sense, this book is the best x DELAY FAULT TESTING FOR VLSI CIRCUITS available guide for an engineer designing or testing VLSI systems. Tech niques for path delay testing and for use of slower test equipment to test high-speed circuits are of particular interest.
Testing Of Digital Systems
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Author : N. K. Jha
language : en
Publisher: Cambridge University Press
Release Date : 2003-05-08
Testing Of Digital Systems written by N. K. Jha and has been published by Cambridge University Press this book supported file pdf, txt, epub, kindle and other format this book has been release on 2003-05-08 with Computers categories.
Device testing represents the single largest manufacturing expense in the semiconductor industry, costing over $40 billion a year. The most comprehensive and wide ranging book of its kind, Testing of Digital Systems covers everything you need to know about this vitally important subject. Starting right from the basics, the authors take the reader through automatic test pattern generation, design for testability and built-in self-test of digital circuits before moving on to more advanced topics such as IDDQ testing, functional testing, delay fault testing, memory testing, and fault diagnosis. The book includes detailed treatment of the latest techniques including test generation for various fault models, discussion of testing techniques at different levels of integrated circuit hierarchy and a chapter on system-on-a-chip test synthesis. Written for students and engineers, it is both an excellent senior/graduate level textbook and a valuable reference.
Defect Oriented Testing For Cmos Analog And Digital Circuits
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Author : Manoj Sachdev
language : en
Publisher: Springer Science & Business Media
Release Date : 2013-06-29
Defect Oriented Testing For Cmos Analog And Digital Circuits written by Manoj Sachdev and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2013-06-29 with Technology & Engineering categories.
Defect oriented testing is expected to play a significant role in coming generations of technology. Smaller feature sizes and larger die sizes will make ICs more sensitive to defects that can not be modeled by traditional fault modeling approaches. Furthermore, with increased level of integration, an IC may contain diverse building blocks. Such blocks include, digital logic, PLAs, volatile and non-volatile memories, and analog interfaces. For such diverse building blocks, traditional fault modeling and test approaches will become increasingly inadequate. Defect oriented testing methods have come a long way from a mere interesting academic exercise to a hard industrial reality. Many factors have contributed to its industrial acceptance. Traditional approaches of testing modern integrated circuits (ICs) have been found to be inadequate in terms of quality and economics of test. In a globally competitive semiconductor market place, overall product quality and economics have become very important objectives. In addition, electronic systems are becoming increasingly complex and demand components of highest possible quality. Testing, in general and, defect oriented testing, in particular, help in realizing these objectives. Defect Oriented Testing for CMOS Analog and Digital Circuits is the first book to provide a complete overview of the subject. It is essential reading for all design and test professionals as well as researchers and students working in the field. `A strength of this book is its breadth. Types of designs considered include analog and digital circuits, programmable logic arrays, and memories. Having a fault model does not automatically provide a test. Sometimes, design for testability hardware is necessary. Many design for testability ideas, supported by experimental evidence, are included.' ... from the Foreword by Vishwani D. Agrawal