Wafer Level Testing And Test Planning For Integrated Circuits
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Wafer Level Testing And Test Planning For Integrated Circuits
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Author :
language : en
Publisher:
Release Date : 2005
Wafer Level Testing And Test Planning For Integrated Circuits written by and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2005 with categories.
The relentless scaling of semiconductor devices and high integration levels have lead to a steady increase in the cost of manufacturing test for integrated circuits (ICs). The higher test cost leads to an increase in the product cost of ICs. Product cost is a major driver in the consumer electronics market, which is characterized by low profit margins and the use of a variety of core-based system-on-chip (SoC) designs. Packaging has also been recognized as a significant contributor to the product cost for SoCs. Packaging cost and the test cost for packaged chips can be reduced significantly by the use of effective test methods at the wafer level, also referred to as wafer sort. Test application time is a major practical constraint for wafer sort, even more than for package test. Therefore, not all the scan-based digital test patterns can be applied to the die under test. This thesis first presents a test-length selection technique for wafer-level testing of core-based SoCs. This optimization technique, which is based on a combination of statistical yield modeling and integer linear programming (ILP), provides the pattern count for each embedded core during wafer sort such that the probability of screening defective dies is maximized for a given upper limit on the SoC test time. A large number of wafer-probe contacts can potentially lead to higher yield loss during wafer sort. An optimization framework is therefore presented to address test access mechanism (TAM) optimization and test-length selection for wafer-level testing, when constraints are placed on the number of number of chip pins that can be contacted. Next, a correlation-based signature analysis technique is presented for mixed-signal test at the wafer-level using low-cost digital testers. The proposed method overcomes the limitations of measurement inaccuracies at the wafer-level. A generic cost model is developed to evaluate the effectiveness of wafer-level testing of analog and digital.
Wafer Level Testing And Test Planning For Integrated Circuits
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Author : Sudarshan Bahukudumbi
language : en
Publisher:
Release Date : 2008
Wafer Level Testing And Test Planning For Integrated Circuits written by Sudarshan Bahukudumbi and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2008 with Electronic dissertations categories.
The relentless scaling of semiconductor devices and high integration levels have lead to a steady increase in the cost of manufacturing test for integrated circuits (ICs). The higher test cost leads to an increase in the product cost of ICs. Product cost is a major driver in the consumer electronics market, which is characterized by low profit margins and the use of a variety of core-based system-on-chip (SoC) designs. Packaging has also been recognized as a significant contributor to the product cost for SoCs. Packaging cost and the test cost for packaged chips can be reduced significantly by the use of effective test methods at the wafer level, also referred to as wafer sort. Test application time is a major practical constraint for wafer sort, even more than for package test. Therefore, not all the scan-based digital test patterns can be applied to the die under test. This thesis first presents a test-length selection technique for wafer-level testing of core-based SoCs. This optimization technique, which is based on a combination of statistical yield modeling and integer linear programming (ILP), provides the pattern count for each embedded core during wafer sort such that the probability of screening defective dies is maximized for a given upper limit on the SoC test time. A large number of wafer-probe contacts can potentially lead to higher yield loss during wafer sort. An optimization framework is therefore presented to address test access mechanism (TAM) optimization and test-length selection for wafer-level testing, when constraints are placed on the number of number of chip pins that can be contacted. Next, a correlation-based signature analysis technique is presented for mixed-signal test at the wafer-level using low-cost digital testers. The proposed method overcomes the limitations of measurement inaccuracies at the wafer-level. A generic cost model is developed to evaluate the effectiveness of wafer-level testing of analog and digital cores in a mixed-signal SoC, and to study its impact on test escapes, yield loss and packaging cost. Results are presented for a typical mixed-signal "big-D/small-A" SoC from industry, which contains a large section of flattened digital logic and several large mixed-signal cores. Wafer-level test during burn-in (WLTBI) is an emerging practice in the semiconductor industry that allows testing to be performed simultaneously with burn-in at the wafer-level. However, the testing of multiple cores of a SoC in parallel during WLTBI leads to constantly-varying device power during the duration of the test. This power variation adversely affects predictions of temperature and the time required for burn-in. A test-scheduling technique is presented for WLTBI of core-based SoCs, where the primary objective is to minimize the variation in power consumption during test. A secondary objective is to minimize the test application time. Finally, this thesis presents a test-pattern ordering technique for WLTBI. The objective here is to minimize the variation in power consumption during test application. The test-pattern ordering problem for WLTBI is solved using ILP and efficient heuristic techniques. The thesis also demonstrates how test-pattern manipulation and pattern-ordering can be combined for WLTBI. Test-pattern manipulation is carried out by carefully filling the don't-care (X) bits in test cubes. The X-fill problem is formulated and solved using an efficient polynomial-time algorithm. In summary, this research is targeted at cost-efficient wafer-level test and burn-in of current- and next-generation semiconductor devices. The proposed techniques are expected to bridge the gap between wafer sort and package test, by providing cost-effective wafer-scale test solutions. The results of this research will lead to higher shipped-product quality, lower product cost, and pave the way for known good die (KGD) devices, especially for emerging technologies such as three-dimensional integrated circuits.
Wafer Level Testing And Test During Burn In For Integrated Circuits
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Author : Sudarshan Bahukudumbi
language : en
Publisher: Artech House
Release Date : 2010
Wafer Level Testing And Test During Burn In For Integrated Circuits written by Sudarshan Bahukudumbi and has been published by Artech House this book supported file pdf, txt, epub, kindle and other format this book has been release on 2010 with Technology & Engineering categories.
Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis of these methods, showing how wafer-level testing during burn-in (WLTBI) helps lower product cost in semiconductor manufacturing. Engineers learn how to implement the testing of integrated circuits at the wafer-level under various resource constraints. Moreover, this unique book helps practitioners address the issue of enabling next generation products with previous generation testers. Practitioners also find expert insights on current industry trends in WLTBI test solutions.
General Society Student Poster Session
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Author : A. H, Suroviec
language : en
Publisher: The Electrochemical Society
Release Date : 2016-09-21
General Society Student Poster Session written by A. H, Suroviec and has been published by The Electrochemical Society this book supported file pdf, txt, epub, kindle and other format this book has been release on 2016-09-21 with Science categories.
Handbook Of Integrated Circuit Industry
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Author : Yangyuan Wang
language : en
Publisher: Springer Nature
Release Date : 2023-11-27
Handbook Of Integrated Circuit Industry written by Yangyuan Wang and has been published by Springer Nature this book supported file pdf, txt, epub, kindle and other format this book has been release on 2023-11-27 with Technology & Engineering categories.
Written by hundreds experts who have made contributions to both enterprise and academics research, these excellent reference books provide all necessary knowledge of the whole industrial chain of integrated circuits, and cover topics related to the technology evolution trends, fabrication, applications, new materials, equipment, economy, investment, and industrial developments of integrated circuits. Especially, the coverage is broad in scope and deep enough for all kind of readers being interested in integrated circuit industry. Remarkable data collection, update marketing evaluation, enough working knowledge of integrated circuit fabrication, clear and accessible category of integrated circuit products, and good equipment insight explanation, etc. can make general readers build up a clear overview about the whole integrated circuit industry. This encyclopedia is designed as a reference book for scientists and engineers actively involved in integrated circuit research and development field. In addition, this book provides enough guide lines and knowledges to benefit enterprisers being interested in integrated circuit industry.
Wafer Level Integrated Systems
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Author : Stuart K. Tewksbury
language : en
Publisher: Springer Science & Business Media
Release Date : 2012-12-06
Wafer Level Integrated Systems written by Stuart K. Tewksbury and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2012-12-06 with Technology & Engineering categories.
From the perspective of complex systems, conventional Ie's can be regarded as "discrete" devices interconnected according to system design objectives imposed at the circuit board level and higher levels in the system implementation hierarchy. However, silicon monolithic circuits have progressed to such complex functions that a transition from a philosophy of integrated circuits (Ie's) to one of integrated sys tems is necessary. Wafer-scale integration has played an important role over the past few years in highlighting the system level issues which will most significantly impact the implementation of complex monolithic systems and system components. Rather than being a revolutionary approach, wafer-scale integration will evolve naturally from VLSI as defect avoidance, fault tolerance and testing are introduced into VLSI circuits. Successful introduction of defect avoidance, for example, relaxes limits imposed by yield and cost on Ie dimensions, allowing the monolithic circuit's area to be chosen according to the natural partitioning of a system into individual functions rather than imposing area limits due to defect densities. The term "wafer level" is perhaps more appropriate than "wafer-scale". A "wafer-level" monolithic system component may have dimensions ranging from conventional yield-limited Ie dimensions to full wafer dimensions. In this sense, "wafer-scale" merely represents the obvious upper practical limit imposed by wafer sizes on the area of monolithic circuits. The transition to monolithic, wafer-level integrated systems will require a mapping of the full range of system design issues onto the design of monolithic circuit.
Proceedings
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Author :
language : en
Publisher:
Release Date : 1982
Proceedings written by and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 1982 with CAD/CAM systems categories.
Design Of 3d Integrated Circuits And Systems
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Author : Rohit Sharma
language : en
Publisher: CRC Press
Release Date : 2018-09-03
Design Of 3d Integrated Circuits And Systems written by Rohit Sharma and has been published by CRC Press this book supported file pdf, txt, epub, kindle and other format this book has been release on 2018-09-03 with Technology & Engineering categories.
Three-dimensional (3D) integration of microsystems and subsystems has become essential to the future of semiconductor technology development. 3D integration requires a greater understanding of several interconnected systems stacked over each other. While this vertical growth profoundly increases the system functionality, it also exponentially increases the design complexity. Design of 3D Integrated Circuits and Systems tackles all aspects of 3D integration, including 3D circuit and system design, new processes and simulation techniques, alternative communication schemes for 3D circuits and systems, application of novel materials for 3D systems, and the thermal challenges to restrict power dissipation and improve performance of 3D systems. Containing contributions from experts in industry as well as academia, this authoritative text: Illustrates different 3D integration approaches, such as die-to-die, die-to-wafer, and wafer-to-wafer Discusses the use of interposer technology and the role of Through-Silicon Vias (TSVs) Presents the latest improvements in three major fields of thermal management for multiprocessor systems-on-chip (MPSoCs) Explores ThruChip Interface (TCI), NAND flash memory stacking, and emerging applications Describes large-scale integration testing and state-of-the-art low-power testing solutions Complete with experimental results of chip-level 3D integration schemes tested at IBM and case studies on advanced complementary metal–oxide–semiconductor (CMOS) integration for 3D integrated circuits (ICs), Design of 3D Integrated Circuits and Systems is a practical reference that not only covers a wealth of design issues encountered in 3D integration but also demonstrates their impact on the efficiency of 3D systems.
Nbs Special Publication
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Author :
language : en
Publisher:
Release Date : 1968
Nbs Special Publication written by and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 1968 with Weights and measures categories.
Defect And Fault Tolerance In Vlsi Systems
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Author : Israel Koren
language : en
Publisher: Springer Science & Business Media
Release Date : 2012-12-06
Defect And Fault Tolerance In Vlsi Systems written by Israel Koren and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2012-12-06 with Computers categories.
This book contains an edited selection of papers presented at the International Workshop on Defect and Fault Tolerance in VLSI Systems held October 6-7, 1988 in Springfield, Massachusetts. Our thanks go to all the contributors and especially the members of the program committee for the difficult and time-consuming work involved in selecting the papers that were presented in the workshop and reviewing the papers included in this book. Thanks are also due to the IEEE Computer Society (in particular, the Technical Committee on Fault-Tolerant Computing and the Technical Committee on VLSI) and the University of Massachusetts at Amherst for sponsoring the workshop, and to the National Science Foundation for supporting (under grant number MIP-8803418) the keynote address and the distribution of this book to all workshop attendees. The objective of the workshop was to bring t. ogether researchers and practition ers from both industry and academia in the field of defect tolerance and yield en ha. ncement in VLSI to discuss their mutual interests in defect-tolerant architectures and models for integrated circuit defects, faults, and yield. Progress in this area was slowed down by the proprietary nature of yield-related data, and by the lack of appropriate forums for disseminating such information. The goal of this workshop was therefore to provide a forum for a dialogue and exchange of views. A follow-up workshop in October 1989, with C. H. Stapper from IBM and V. K. Jain from the University of South Florida as general co-chairmen, is being organized.