Wafer Level Testing And Test During Burn In For Integrated Circuits
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Wafer Level Testing And Test During Burn In For Integrated Circuits
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Author : Sudarshan Bahukudumbi
language : en
Publisher: Artech House
Release Date : 2010
Wafer Level Testing And Test During Burn In For Integrated Circuits written by Sudarshan Bahukudumbi and has been published by Artech House this book supported file pdf, txt, epub, kindle and other format this book has been release on 2010 with Technology & Engineering categories.
Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis of these methods, showing how wafer-level testing during burn-in (WLTBI) helps lower product cost in semiconductor manufacturing. Engineers learn how to implement the testing of integrated circuits at the wafer-level under various resource constraints. Moreover, this unique book helps practitioners address the issue of enabling next generation products with previous generation testers. Practitioners also find expert insights on current industry trends in WLTBI test solutions.
Wafer Level Testing And Test Planning For Integrated Circuits
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Author : Sudarshan Bahukudumbi
language : en
Publisher:
Release Date : 2008
Wafer Level Testing And Test Planning For Integrated Circuits written by Sudarshan Bahukudumbi and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2008 with Electronic dissertations categories.
The relentless scaling of semiconductor devices and high integration levels have lead to a steady increase in the cost of manufacturing test for integrated circuits (ICs). The higher test cost leads to an increase in the product cost of ICs. Product cost is a major driver in the consumer electronics market, which is characterized by low profit margins and the use of a variety of core-based system-on-chip (SoC) designs. Packaging has also been recognized as a significant contributor to the product cost for SoCs. Packaging cost and the test cost for packaged chips can be reduced significantly by the use of effective test methods at the wafer level, also referred to as wafer sort. Test application time is a major practical constraint for wafer sort, even more than for package test. Therefore, not all the scan-based digital test patterns can be applied to the die under test. This thesis first presents a test-length selection technique for wafer-level testing of core-based SoCs. This optimization technique, which is based on a combination of statistical yield modeling and integer linear programming (ILP), provides the pattern count for each embedded core during wafer sort such that the probability of screening defective dies is maximized for a given upper limit on the SoC test time. A large number of wafer-probe contacts can potentially lead to higher yield loss during wafer sort. An optimization framework is therefore presented to address test access mechanism (TAM) optimization and test-length selection for wafer-level testing, when constraints are placed on the number of number of chip pins that can be contacted. Next, a correlation-based signature analysis technique is presented for mixed-signal test at the wafer-level using low-cost digital testers. The proposed method overcomes the limitations of measurement inaccuracies at the wafer-level. A generic cost model is developed to evaluate the effectiveness of wafer-level testing of analog and digital cores in a mixed-signal SoC, and to study its impact on test escapes, yield loss and packaging cost. Results are presented for a typical mixed-signal "big-D/small-A" SoC from industry, which contains a large section of flattened digital logic and several large mixed-signal cores. Wafer-level test during burn-in (WLTBI) is an emerging practice in the semiconductor industry that allows testing to be performed simultaneously with burn-in at the wafer-level. However, the testing of multiple cores of a SoC in parallel during WLTBI leads to constantly-varying device power during the duration of the test. This power variation adversely affects predictions of temperature and the time required for burn-in. A test-scheduling technique is presented for WLTBI of core-based SoCs, where the primary objective is to minimize the variation in power consumption during test. A secondary objective is to minimize the test application time. Finally, this thesis presents a test-pattern ordering technique for WLTBI. The objective here is to minimize the variation in power consumption during test application. The test-pattern ordering problem for WLTBI is solved using ILP and efficient heuristic techniques. The thesis also demonstrates how test-pattern manipulation and pattern-ordering can be combined for WLTBI. Test-pattern manipulation is carried out by carefully filling the don't-care (X) bits in test cubes. The X-fill problem is formulated and solved using an efficient polynomial-time algorithm. In summary, this research is targeted at cost-efficient wafer-level test and burn-in of current- and next-generation semiconductor devices. The proposed techniques are expected to bridge the gap between wafer sort and package test, by providing cost-effective wafer-scale test solutions. The results of this research will lead to higher shipped-product quality, lower product cost, and pave the way for known good die (KGD) devices, especially for emerging technologies such as three-dimensional integrated circuits.
On Wafer Microwave Measurements And De Embedding
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Author : Errikos Lourandakis
language : en
Publisher: Artech House
Release Date : 2016-07-31
On Wafer Microwave Measurements And De Embedding written by Errikos Lourandakis and has been published by Artech House this book supported file pdf, txt, epub, kindle and other format this book has been release on 2016-07-31 with Technology & Engineering categories.
This new authoritative resource presents the basics of network analyzer measurement equipment and troubleshooting errors involved in the on-wafer microwave measurement process. This book bridges the gap between theoretical and practical information using real-world practices that address all aspects of on-wafer passive device characterization in the microwave frequency range up to 60GHz. Readers find data and measurements from silicon integrated passive devices fabricated and tested in advance CMOS technologies. Basic circuit equations, terms and fundamentals of time and frequency domain analysis are covered. This book also explores the basics of vector network analyzers (VNA), two port S-parameter measurement routines, signal flow graphs, network theory, error models and VNA calibrations with the use of calibration standards.
Wafer Level Integrated Systems
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Author : Stuart K. Tewksbury
language : en
Publisher: Springer Science & Business Media
Release Date : 2012-12-06
Wafer Level Integrated Systems written by Stuart K. Tewksbury and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2012-12-06 with Technology & Engineering categories.
From the perspective of complex systems, conventional Ie's can be regarded as "discrete" devices interconnected according to system design objectives imposed at the circuit board level and higher levels in the system implementation hierarchy. However, silicon monolithic circuits have progressed to such complex functions that a transition from a philosophy of integrated circuits (Ie's) to one of integrated sys tems is necessary. Wafer-scale integration has played an important role over the past few years in highlighting the system level issues which will most significantly impact the implementation of complex monolithic systems and system components. Rather than being a revolutionary approach, wafer-scale integration will evolve naturally from VLSI as defect avoidance, fault tolerance and testing are introduced into VLSI circuits. Successful introduction of defect avoidance, for example, relaxes limits imposed by yield and cost on Ie dimensions, allowing the monolithic circuit's area to be chosen according to the natural partitioning of a system into individual functions rather than imposing area limits due to defect densities. The term "wafer level" is perhaps more appropriate than "wafer-scale". A "wafer-level" monolithic system component may have dimensions ranging from conventional yield-limited Ie dimensions to full wafer dimensions. In this sense, "wafer-scale" merely represents the obvious upper practical limit imposed by wafer sizes on the area of monolithic circuits. The transition to monolithic, wafer-level integrated systems will require a mapping of the full range of system design issues onto the design of monolithic circuit.
Labs On Chip
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Author : Eugenio Iannone
language : en
Publisher: CRC Press
Release Date : 2018-09-03
Labs On Chip written by Eugenio Iannone and has been published by CRC Press this book supported file pdf, txt, epub, kindle and other format this book has been release on 2018-09-03 with Medical categories.
Labs on Chip: Principles, Design and Technology provides a complete reference for the complex field of labs on chip in biotechnology. Merging three main areas— fluid dynamics, monolithic micro- and nanotechnology, and out-of-equilibrium biochemistry—this text integrates coverage of technology issues with strong theoretical explanations of design techniques. Analyzing each subject from basic principles to relevant applications, this book: Describes the biochemical elements required to work on labs on chip Discusses fabrication, microfluidic, and electronic and optical detection techniques Addresses planar technologies, polymer microfabrication, and process scalability to huge volumes Presents a global view of current lab-on-chip research and development Devotes an entire chapter to labs on chip for genetics Summarizing in one source the different technical competencies required, Labs on Chip: Principles, Design and Technology offers valuable guidance for the lab-on-chip design decision-making process, while exploring essential elements of labs on chip useful both to the professional who wants to approach a new field and to the specialist who wants to gain a broader perspective.
Thermal Issues In Testing Of Advanced Systems On Chip
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Author : Nima Aghaee Ghaleshahi
language : en
Publisher: Linköping University Electronic Press
Release Date : 2015-09-23
Thermal Issues In Testing Of Advanced Systems On Chip written by Nima Aghaee Ghaleshahi and has been published by Linköping University Electronic Press this book supported file pdf, txt, epub, kindle and other format this book has been release on 2015-09-23 with categories.
Many cutting-edge computer and electronic products are powered by advanced Systems-on-Chip (SoC). Advanced SoCs encompass superb performance together with large number of functions. This is achieved by efficient integration of huge number of transistors. Such very large scale integration is enabled by a core-based design paradigm as well as deep-submicron and 3D-stacked-IC technologies. These technologies are susceptible to reliability and testing complications caused by thermal issues. Three crucial thermal issues related to temperature variations, temperature gradients, and temperature cycling are addressed in this thesis. Existing test scheduling techniques rely on temperature simulations to generate schedules that meet thermal constraints such as overheating prevention. The difference between the simulated temperatures and the actual temperatures is called temperature error. This error, for past technologies, is negligible. However, advanced SoCs experience large errors due to large process variations. Such large errors have costly consequences, such as overheating, and must be taken care of. This thesis presents an adaptive approach to generate test schedules that handle such temperature errors. Advanced SoCs manufactured as 3D stacked ICs experience large temperature gradients. Temperature gradients accelerate certain early-life defect mechanisms. These mechanisms can be artificially accelerated using gradient-based, burn-in like, operations so that the defects are detected before shipping. Moreover, temperature gradients exacerbate some delay-related defects. In order to detect such defects, testing must be performed when appropriate temperature-gradients are enforced. A schedule-based technique that enforces the temperature-gradients for burn-in like operations is proposed in this thesis. This technique is further developed to support testing for delay-related defects while appropriate gradients are enforced. The last thermal issue addressed by this thesis is related to temperature cycling. Temperature cycling test procedures are usually applied to safety-critical applications to detect cycling-related early-life failures. Such failures affect advanced SoCs, particularly through-silicon-via structures in 3D-stacked-ICs. An efficient schedule-based cycling-test technique that combines cycling acceleration with testing is proposed in this thesis. The proposed technique fits into existing 3D testing procedures and does not require temperature chambers. Therefore, the overall cycling acceleration and testing cost can be drastically reduced. All the proposed techniques have been implemented and evaluated with extensive experiments based on ITC’02 benchmarks as well as a number of 3D stacked ICs. Experiments show that the proposed techniques work effectively and reduce the costs, in particular the costs related to addressing thermal issues and early-life failures. We have also developed a fast temperature simulation technique based on a closed-form solution for the temperature equations. Experiments demonstrate that the proposed simulation technique reduces the schedule generation time by more than half.
Microelectronics Failure Analysis
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Author : EDFAS Desk Reference Committee
language : en
Publisher: ASM International
Release Date : 2011
Microelectronics Failure Analysis written by EDFAS Desk Reference Committee and has been published by ASM International this book supported file pdf, txt, epub, kindle and other format this book has been release on 2011 with Technology & Engineering categories.
Includes bibliographical references and index.
Layout Techniques For Integrated Circuit Designers
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Author : Mikael Sahrling
language : en
Publisher: Artech House
Release Date : 2022-08-31
Layout Techniques For Integrated Circuit Designers written by Mikael Sahrling and has been published by Artech House this book supported file pdf, txt, epub, kindle and other format this book has been release on 2022-08-31 with Technology & Engineering categories.
This book provides complete step-by-step guidance on the physical implementation of modern integrated circuits, showing you their limitations and guiding you through their common remedies. The book describes today’s manufacturing techniques and how they impact design rules. You will understand how to build common high frequency devices such as inductors, capacitors and T-coils, and will also learn strategies for dealing with high-speed routing both on package level and on-chip applications. Numerous algorithms implemented in Python are provided to guide you through how extraction, netlist comparison and design rule checkers can be built. The book also helps you unravel complexities that effect circuit design, including signal integrity, matching, IR drop, parasitic impedance and more, saving you time in addressing these effects directly. You will also find detailed descriptions of software tools used to analyze a layout database, showing you how devices can be recognized and connectivity accurately assessed. The book removes much of fog that often hides the inner workings of layout related software tools and helps you better understand: the physics of advanced nodes, high speed techniques used in modern integrated technologies, and the inner working of software used to analyze layout databases. This is an excellent resource for circuit designers implementing a schematic in a layout database, especially those involved in deep submicron designs, as well as layout designers wishing to deepen their understanding of modern layout rules.
Integrated Circuit Test Engineering
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Author : Ian A. Grout
language : en
Publisher: Springer Science & Business Media
Release Date : 2005-08-22
Integrated Circuit Test Engineering written by Ian A. Grout and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2005-08-22 with Technology & Engineering categories.
Using the book and the software provided with it, the reader can build his/her own tester arrangement to investigate key aspects of analog-, digital- and mixed system circuits Plan of attack based on traditional testing, circuit design and circuit manufacture allows the reader to appreciate a testing regime from the point of view of all the participating interests Worked examples based on theoretical bookwork, practical experimentation and simulation exercises teach the reader how to test circuits thoroughly and effectively
Lab On A Chip
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Author : Yehya H. Ghallab
language : en
Publisher: Artech House
Release Date : 2010
Lab On A Chip written by Yehya H. Ghallab and has been published by Artech House this book supported file pdf, txt, epub, kindle and other format this book has been release on 2010 with Biomedical engineering categories.
HereOCOs a groundbreaking book that introduces and discusses the important aspects of lab-on-a-chip, including the practical techniques, circuits, microsystems, and key applications in the biomedical, biology, and life science fields. Moreover, this volume covers ongoing research in lab-on-a-chip integration and electric field imaging. Presented in a clear and logical manner, the book provides you with the fundamental underpinnings of lab-on-a-chip, presents practical results, and brings you up to date with state-of-the-art research in the field. This unique resource is supported with over 160 illustrations that clarify important topics throughout.