Power Constrained Testing Of Vlsi Circuits
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Power Constrained Testing Of Vlsi Circuits
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Author : Nicola Nicolici
language : en
Publisher: Springer Science & Business Media
Release Date : 2006-04-11
Power Constrained Testing Of Vlsi Circuits written by Nicola Nicolici and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2006-04-11 with Technology & Engineering categories.
This text focuses on techniques for minimizing power dissipation during test application at logic and register-transfer levels of abstraction of the VLSI design flow. It surveys existing techniques and presents several test automation techniques for reducing power in scan-based sequential circuits and BIST data paths.
Power Constrained Testing Of Vlsi Circuits
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Author : Nicola Nicolici
language : en
Publisher: Springer Science & Business Media
Release Date : 2003-02-28
Power Constrained Testing Of Vlsi Circuits written by Nicola Nicolici and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2003-02-28 with Computers categories.
This text focuses on techniques for minimizing power dissipation during test application at logic and register-transfer levels of abstraction of the VLSI design flow. It surveys existing techniques and presents several test automation techniques for reducing power in scan-based sequential circuits and BIST data paths.
Introduction To Advanced System On Chip Test Design And Optimization
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Author : Erik Larsson
language : en
Publisher: Springer Science & Business Media
Release Date : 2006-03-30
Introduction To Advanced System On Chip Test Design And Optimization written by Erik Larsson and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2006-03-30 with Technology & Engineering categories.
SOC test design and its optimization is the topic of Introduction to Advanced System-on-Chip Test Design and Optimization. It gives an introduction to testing, describes the problems related to SOC testing, discusses the modeling granularity and the implementation into EDA (electronic design automation) tools. The book is divided into three sections: i) test concepts, ii) SOC design for test, and iii) SOC test applications. The first part covers an introduction into test problems including faults, fault types, design-flow, design-for-test techniques such as scan-testing and Boundary Scan. The second part of the book discusses SOC related problems such as system modeling, test conflicts, power consumption, test access mechanism design, test scheduling and defect-oriented scheduling. Finally, the third part focuses on SOC applications, such as integrated test scheduling and TAM design, defect-oriented scheduling, and integrating test design with the core selection process.
Thermal Aware Testing Of Digital Vlsi Circuits And Systems
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Author : Santanu Chattopadhyay
language : en
Publisher: CRC Press
Release Date : 2018-04-24
Thermal Aware Testing Of Digital Vlsi Circuits And Systems written by Santanu Chattopadhyay and has been published by CRC Press this book supported file pdf, txt, epub, kindle and other format this book has been release on 2018-04-24 with Technology & Engineering categories.
This book aims to highlight the research activities in the domain of thermal-aware testing. Thermal-aware testing can be employed both at circuit level and at system level Describes range of algorithms for addressing thermal-aware test issue, presents comparison of temperature reduction with power-aware techniques and include results on benchmark circuits and systems for different techniques This book will be suitable for researchers working on power- and thermal-aware design and the testing of digital VLSI chips
Cmos Sram Circuit Design And Parametric Test In Nano Scaled Technologies
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Author : Andrei Pavlov
language : en
Publisher: Springer Science & Business Media
Release Date : 2008-06-01
Cmos Sram Circuit Design And Parametric Test In Nano Scaled Technologies written by Andrei Pavlov and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2008-06-01 with Technology & Engineering categories.
The monograph will be dedicated to SRAM (memory) design and test issues in nano-scaled technologies by adapting the cell design and chip design considerations to the growing process variations with associated test issues. Purpose: provide process-aware solutions for SRAM design and test challenges.
Wafer Level Testing And Test During Burn In For Integrated Circuits
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Author : Sudarshan Bahukudumbi
language : en
Publisher: Artech House
Release Date : 2010
Wafer Level Testing And Test During Burn In For Integrated Circuits written by Sudarshan Bahukudumbi and has been published by Artech House this book supported file pdf, txt, epub, kindle and other format this book has been release on 2010 with Technology & Engineering categories.
Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis of these methods, showing how wafer-level testing during burn-in (WLTBI) helps lower product cost in semiconductor manufacturing. Engineers learn how to implement the testing of integrated circuits at the wafer-level under various resource constraints. Moreover, this unique book helps practitioners address the issue of enabling next generation products with previous generation testers. Practitioners also find expert insights on current industry trends in WLTBI test solutions.
Soc System On A Chip Testing For Plug And Play Test Automation
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Author : Krishnendu Chakrabarty
language : en
Publisher: Springer Science & Business Media
Release Date : 2013-04-17
Soc System On A Chip Testing For Plug And Play Test Automation written by Krishnendu Chakrabarty and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2013-04-17 with Technology & Engineering categories.
System-on-a-Chip (SOC) integrated circuits composed of embedded cores are now commonplace. Nevertheless, there remain several roadblocks to rapid and efficient system integration. Test development is seen as a major bottleneck in SOC design and manufacturing capabilities. Testing SOCs is especially challenging in the absence of standardized test structures, test automation tools, and test protocols. In addition, long interconnects, high density, and high-speed designs lead to new types of faults involving crosstalk and signal integrity. SOC (System-on-a-Chip) Testing for Plug and Play Test Automation is an edited work containing thirteen contributions that address various aspects of SOC testing. SOC (System-on-a-Chip) Testing for Plug and Play Test Automation is a valuable reference for researchers and students interested in various aspects of SOC testing.
Oscillation Based Test In Mixed Signal Circuits
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Author : Gloria Huertas Sánchez
language : en
Publisher: Springer Science & Business Media
Release Date : 2007-06-03
Oscillation Based Test In Mixed Signal Circuits written by Gloria Huertas Sánchez and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2007-06-03 with Technology & Engineering categories.
This book presents the development and experimental validation of the structural test strategy called Oscillation-Based Test – OBT in short. The results presented here assert, not only from a theoretical point of view, but also based on a wide experimental support, that OBT is an efficient defect-oriented test solution, complementing the existing functional test techniques for mixed-signal circuits.
Thermal Issues In Testing Of Advanced Systems On Chip
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Author : Nima Aghaee Ghaleshahi
language : en
Publisher: Linköping University Electronic Press
Release Date : 2015-09-23
Thermal Issues In Testing Of Advanced Systems On Chip written by Nima Aghaee Ghaleshahi and has been published by Linköping University Electronic Press this book supported file pdf, txt, epub, kindle and other format this book has been release on 2015-09-23 with categories.
Many cutting-edge computer and electronic products are powered by advanced Systems-on-Chip (SoC). Advanced SoCs encompass superb performance together with large number of functions. This is achieved by efficient integration of huge number of transistors. Such very large scale integration is enabled by a core-based design paradigm as well as deep-submicron and 3D-stacked-IC technologies. These technologies are susceptible to reliability and testing complications caused by thermal issues. Three crucial thermal issues related to temperature variations, temperature gradients, and temperature cycling are addressed in this thesis. Existing test scheduling techniques rely on temperature simulations to generate schedules that meet thermal constraints such as overheating prevention. The difference between the simulated temperatures and the actual temperatures is called temperature error. This error, for past technologies, is negligible. However, advanced SoCs experience large errors due to large process variations. Such large errors have costly consequences, such as overheating, and must be taken care of. This thesis presents an adaptive approach to generate test schedules that handle such temperature errors. Advanced SoCs manufactured as 3D stacked ICs experience large temperature gradients. Temperature gradients accelerate certain early-life defect mechanisms. These mechanisms can be artificially accelerated using gradient-based, burn-in like, operations so that the defects are detected before shipping. Moreover, temperature gradients exacerbate some delay-related defects. In order to detect such defects, testing must be performed when appropriate temperature-gradients are enforced. A schedule-based technique that enforces the temperature-gradients for burn-in like operations is proposed in this thesis. This technique is further developed to support testing for delay-related defects while appropriate gradients are enforced. The last thermal issue addressed by this thesis is related to temperature cycling. Temperature cycling test procedures are usually applied to safety-critical applications to detect cycling-related early-life failures. Such failures affect advanced SoCs, particularly through-silicon-via structures in 3D-stacked-ICs. An efficient schedule-based cycling-test technique that combines cycling acceleration with testing is proposed in this thesis. The proposed technique fits into existing 3D testing procedures and does not require temperature chambers. Therefore, the overall cycling acceleration and testing cost can be drastically reduced. All the proposed techniques have been implemented and evaluated with extensive experiments based on ITC’02 benchmarks as well as a number of 3D stacked ICs. Experiments show that the proposed techniques work effectively and reduce the costs, in particular the costs related to addressing thermal issues and early-life failures. We have also developed a fast temperature simulation technique based on a closed-form solution for the temperature equations. Experiments demonstrate that the proposed simulation technique reduces the schedule generation time by more than half.
Emerging Nanotechnologies
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Author : Mohammad Tehranipoor
language : en
Publisher: Springer Science & Business Media
Release Date : 2007-12-08
Emerging Nanotechnologies written by Mohammad Tehranipoor and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2007-12-08 with Technology & Engineering categories.
Emerging Nanotechnologies: Test, Defect Tolerance and Reliability covers various technologies that have been developing over the last decades such as chemically assembled electronic nanotechnology, Quantum-dot Cellular Automata (QCA), and nanowires and carbon nanotubes. Each of these technologies offers various advantages and disadvantages. Some suffer from high power, some work in very low temperatures and some others need indeterministic bottom-up assembly. These emerging technologies are not considered as a direct replacement for CMOS technology and may require a completely new architecture to achieve their functionality. Emerging Nanotechnologies: Test, Defect Tolerance and Reliability brings all of these issues together in one place for readers and researchers who are interested in this rapidly changing field.