Testing Static Random Access Memories

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Testing Static Random Access Memories

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Author : Said Hamdioui
language : en
Publisher: Springer Science & Business Media
Release Date : 2004-03-31

Testing Static Random Access Memories written by Said Hamdioui and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2004-03-31 with Computers categories.

Embedded memories are one of the fastest growing segments oftoday's new technology market. According to the 2001 InternationalTechnology Roadmap for Semiconductors, embedded memories will continueto dominate the increasing system on chip (SoC) content in the nextseveral years, approaching 94% of the SoC area in about 10 years.Furthermore, the shrinking size of manufacturing structures makesmemories more sensitive to defects. Consequently, the memory yieldwill have a dramatic impact on the overall Defect-per-million level, hence on the overall SoC yield. Meeting a high memory yield requiresunderstanding memory designs, modeling their faulty behaviors, designing adequate tests and diagnosis algorithms as well as efficientself-test and repair schemes."Testing Static Random Access Memories" covers testing of one ofthe important semiconductor memories types; it address testing ofstatic random access memories (SRAMs), both single-port andmulti-port. It contributes to the technical acknowledge needed bythose involved in memory testing, engineers and researchers. The bookbegins with outlining the most popular SRAMs architectures. Then, thedescription of realistic fault models, based on defect injection andSPICE simulation, are introduced. Thereafter, high quality and lowcost test patterns, as well as test strategies for single-port, two-port and any p-port SRAMs are presented, together with somepreliminary test results showing the importance of the new tests inreducing DPM level. The impact of the port restrictions (e.g., read-only ports) on the fault models, tests, and test strategies isalso discussed.Features:

High Performance Memory Testing

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Author : R. Dean Adams
language : en
Publisher: Springer Science & Business Media
Release Date : 2005-12-29

High Performance Memory Testing written by R. Dean Adams and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2005-12-29 with Technology & Engineering categories.

Are memory applications more critical than they have been in the past? Yes, but even more critical is the number of designs and the sheer number of bits on each design. It is assured that catastrophes, which were avoided in the past because memories were small, will easily occur if the design and test engineers do not do their jobs very carefully. High Performance Memory Testing: Design Principles, Fault Modeling and Self Test is based on the author's 20 years of experience in memory design, memory reliability development and memory self test. High Performance Memory Testing: Design Principles, Fault Modeling and Self Test is written for the professional and the researcher to help them understand the memories that are being tested.

Advanced Test Methods For Srams

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Author : Alberto Bosio
language : en
Publisher: Springer Science & Business Media
Release Date : 2009-10-08

Advanced Test Methods For Srams written by Alberto Bosio and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2009-10-08 with Technology & Engineering categories.

Modern electronics depend on nanoscaled technologies that present new challenges in terms of testing and diagnostics. Memories are particularly prone to defects since they exploit the technology limits to get the highest density. This book is an invaluable guide to the testing and diagnostics of the latest generation of SRAM, one of the most widely applied types of memory. Classical methods for testing memory are designed to handle the so-called "static faults," but these test solutions are not sufficient for faults that are emerging in the latest Very Deep Sub-Micron (VDSM) technologies. These new fault models, referred to as "dynamic faults", are not covered by classical test solutions and require the dedicated test sequences presented in this book.

Essentials Of Electronic Testing For Digital Memory And Mixed Signal Vlsi Circuits

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Author : M. Bushnell
language : en
Publisher: Springer Science & Business Media
Release Date : 2006-04-11

Essentials Of Electronic Testing For Digital Memory And Mixed Signal Vlsi Circuits written by M. Bushnell and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2006-04-11 with Technology & Engineering categories.

The modern electronic testing has a forty year history. Test professionals hold some fairly large conferences and numerous workshops, have a journal, and there are over one hundred books on testing. Still, a full course on testing is offered only at a few universities, mostly by professors who have a research interest in this area. Apparently, most professors would not have taken a course on electronic testing when they were students. Other than the computer engineering curriculum being too crowded, the major reason cited for the absence of a course on electronic testing is the lack of a suitable textbook. For VLSI the foundation was provided by semiconductor device techn- ogy, circuit design, and electronic testing. In a computer engineering curriculum, therefore, it is necessary that foundations should be taught before applications. The field of VLSI has expanded to systems-on-a-chip, which include digital, memory, and mixed-signalsubsystems. To our knowledge this is the first textbook to cover all three types of electronic circuits. We have written this textbook for an undergraduate “foundations” course on electronic testing. Obviously, it is too voluminous for a one-semester course and a teacher will have to select from the topics. We did not restrict such freedom because the selection may depend upon the individual expertise and interests. Besides, there is merit in having a larger book that will retain its usefulness for the owner even after the completion of the course. With equal tenacity, we address the needs of three other groups of readers.

Vlsi Test Principles And Architectures

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Author : Laung-Terng Wang
language : en
Publisher: Elsevier
Release Date : 2006-08-14

Vlsi Test Principles And Architectures written by Laung-Terng Wang and has been published by Elsevier this book supported file pdf, txt, epub, kindle and other format this book has been release on 2006-08-14 with Technology & Engineering categories.

This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. - Most up-to-date coverage of design for testability. - Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. - Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.

Defect Oriented Testing For Cmos Analog And Digital Circuits

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Author : Manoj Sachdev
language : en
Publisher: Springer Science & Business Media
Release Date : 2013-06-29

Defect Oriented Testing For Cmos Analog And Digital Circuits written by Manoj Sachdev and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2013-06-29 with Technology & Engineering categories.

Defect oriented testing is expected to play a significant role in coming generations of technology. Smaller feature sizes and larger die sizes will make ICs more sensitive to defects that can not be modeled by traditional fault modeling approaches. Furthermore, with increased level of integration, an IC may contain diverse building blocks. Such blocks include, digital logic, PLAs, volatile and non-volatile memories, and analog interfaces. For such diverse building blocks, traditional fault modeling and test approaches will become increasingly inadequate. Defect oriented testing methods have come a long way from a mere interesting academic exercise to a hard industrial reality. Many factors have contributed to its industrial acceptance. Traditional approaches of testing modern integrated circuits (ICs) have been found to be inadequate in terms of quality and economics of test. In a globally competitive semiconductor market place, overall product quality and economics have become very important objectives. In addition, electronic systems are becoming increasingly complex and demand components of highest possible quality. Testing, in general and, defect oriented testing, in particular, help in realizing these objectives. Defect Oriented Testing for CMOS Analog and Digital Circuits is the first book to provide a complete overview of the subject. It is essential reading for all design and test professionals as well as researchers and students working in the field. `A strength of this book is its breadth. Types of designs considered include analog and digital circuits, programmable logic arrays, and memories. Having a fault model does not automatically provide a test. Sometimes, design for testability hardware is necessary. Many design for testability ideas, supported by experimental evidence, are included.' ... from the Foreword by Vishwani D. Agrawal

Digital Timing Measurements

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Author : Wolfgang Maichen
language : en
Publisher: Springer Science & Business Media
Release Date : 2006-10-03

Digital Timing Measurements written by Wolfgang Maichen and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2006-10-03 with Technology & Engineering categories.

As many circuits and applications now enter the Gigahertz frequency range, accurate digital timing measurements have become crucial in the design, verification, characterization, and application of electronic circuits. To be successful in this endeavour, an engineer needs a knowledge base covering instrumentation, measurement techniques, signal integrity, jitter and timing concepts, and statistics. Very often even the most experienced digital test engineers, while mastering some of those subjects, lack systematic knowledge or experience in the high speed signal area. Digital Timing Measurements gives a compact, practice-oriented overview on all those subjects. The emphasis is on useable concepts and real-life guidelines that can be readily put into practice, with references to the underlying mathematical theory. It unites in one place a variety of information relevant to high speed testing, measurement, signal fidelity, and instrumentation.

Digital Logic Testing And Simulation

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Author : Alexander Miczo
language : en
Publisher: John Wiley & Sons
Release Date : 2003-10-24

Digital Logic Testing And Simulation written by Alexander Miczo and has been published by John Wiley & Sons this book supported file pdf, txt, epub, kindle and other format this book has been release on 2003-10-24 with Technology & Engineering categories.

Your road map for meeting today's digital testing challenges Today, digital logic devices are common in products that impact public safety, including applications in transportation and human implants. Accurate testing has become more critical to reliability, safety, and the bottom line. Yet, as digital systems become more ubiquitous and complex, the challenge of testing them has become more difficult. As one development group designing a RISC stated, "the work required to . . . test a chip of this size approached the amount of effort required to design it." A valued reference for nearly two decades, Digital Logic Testing and Simulation has been significantly revised and updated for designers and test engineers who must meet this challenge. There is no single solution to the testing problem. Organized in an easy-to-follow, sequential format, this Second Edition familiarizes the reader with the many different strategies for testing and their applications, and assesses the strengths and weaknesses of the various approaches. The book reviews the building blocks of a successful testing strategy and guides the reader on choosing the best solution for a particular application. Digital Logic Testing and Simulation, Second Edition covers such key topics as: * Binary Decision Diagrams (BDDs) and cycle-based simulation * Tester architectures/Standard Test Interface Language (STIL) * Practical algorithms written in a Hardware Design Language (HDL) * Fault tolerance * Behavioral Automatic Test Pattern Generation (ATPG) * The development of the Test Design Expert (TDX), the many obstacles encountered and lessons learned in creating this novel testing approach Up-to-date and comprehensive, Digital Logic Testing and Simulation is an important resource for anyone charged with pinpointing faulty products and assuring quality, safety, and profitability.

Fault Tolerance Techniques For Sram Based Fpgas

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Author : Fernanda Lima Kastensmidt
language : en
Publisher: Springer Science & Business Media
Release Date : 2007-02-01

Fault Tolerance Techniques For Sram Based Fpgas written by Fernanda Lima Kastensmidt and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2007-02-01 with Technology & Engineering categories.

Fault-tolerance in integrated circuits is not an exclusive concern regarding space designers or highly-reliable application engineers. Rather, designers of next generation products must cope with reduced margin noises due to technological advances. The continuous evolution of the fabrication technology process of semiconductor components, in terms of transistor geometry shrinking, power supply, speed, and logic density, has significantly reduced the reliability of very deep submicron integrated circuits, in face of the various internal and external sources of noise. The very popular Field Programmable Gate Arrays, customizable by SRAM cells, are a consequence of the integrated circuit evolution with millions of memory cells to implement the logic, embedded memories, routing, and more recently with embedded microprocessors cores. These re-programmable systems-on-chip platforms must be fault-tolerant to cope with present days requirements. This book discusses fault-tolerance techniques for SRAM-based Field Programmable Gate Arrays (FPGAs). It starts by showing the model of the problem and the upset effects in the programmable architecture. In the sequence, it shows the main fault tolerance techniques used nowadays to protect integrated circuits against errors. A large set of methods for designing fault tolerance systems in SRAM-based FPGAs is described. Some presented techniques are based on developing a new fault-tolerant architecture with new robustness FPGA elements. Other techniques are based on protecting the high-level hardware description before the synthesis in the FPGA. The reader has the flexibility of choosing the most suitable fault-tolerance technique for its project and to compare a set of fault tolerant techniques for programmable logic applications.

Emerging Nanotechnologies

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Author : Mohammad Tehranipoor
language : en
Publisher: Springer Science & Business Media
Release Date : 2007-12-08

Emerging Nanotechnologies written by Mohammad Tehranipoor and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2007-12-08 with Technology & Engineering categories.

Emerging Nanotechnologies: Test, Defect Tolerance and Reliability covers various technologies that have been developing over the last decades such as chemically assembled electronic nanotechnology, Quantum-dot Cellular Automata (QCA), and nanowires and carbon nanotubes. Each of these technologies offers various advantages and disadvantages. Some suffer from high power, some work in very low temperatures and some others need indeterministic bottom-up assembly. These emerging technologies are not considered as a direct replacement for CMOS technology and may require a completely new architecture to achieve their functionality. Emerging Nanotechnologies: Test, Defect Tolerance and Reliability brings all of these issues together in one place for readers and researchers who are interested in this rapidly changing field.