Digital Background Calibration Of Analog To Digital Converters

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Digital Background Calibration Of Analog To Digital Converters

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Author : Bahar Jalali-Farahani
language : en
Publisher: Springer
Release Date : 2013

Digital Background Calibration Of Analog To Digital Converters written by Bahar Jalali-Farahani and has been published by Springer this book supported file pdf, txt, epub, kindle and other format this book has been release on 2013 with Technology & Engineering categories.

Digital Background Calibration of Analog to Digital Converters takes a deep look at the digital calibration techniques in analog-to-digital converters. The problem of compensating for analog circuits impairments is divided into a system identification problem and an error compensation problem. Different approaches in modelling the analog impairments are discussed. Although Digital Background Calibration of Analog to Digital Converters focuses on two popular types of ADCs mainly: Pipeline and Sigma Delta the techniques can be easily used for any analog and mixed-signal design. Design examples are provided that support the theory and show the application of these techniques in designing high performance data acquisitions systems for wireless communication systems, bio-implantable devices and space electronics.

Background Calibration Of Time Interleaved Data Converters

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Author : Manar El-Chammas
language : en
Publisher: Springer Science & Business Media
Release Date : 2011-12-17

Background Calibration Of Time Interleaved Data Converters written by Manar El-Chammas and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2011-12-17 with Technology & Engineering categories.

This book describes techniques for time-interleaving a number of analog-to-digital data converters to achieve demanding bandwidth requirements. Readers will benefit from the presentation of a low-power solution that can be used in actual products, while alleviating the time-varying signal artifacts that typically arise when implementing such a system architecture.

A Calibration Service For Analog To Digital And Digital To Analog Converters

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Author : T. Michael Souders
language : en
Publisher:
Release Date : 1981

A Calibration Service For Analog To Digital And Digital To Analog Converters written by T. Michael Souders and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 1981 with Analog-to-digital converters categories.

A Background Digital Calibration Technique For Oversampling Delta Sigma Analog To Digital Converters With 2 Bit Internal Quantizers

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Author : José S. Niell
language : en
Publisher:
Release Date : 1995

A Background Digital Calibration Technique For Oversampling Delta Sigma Analog To Digital Converters With 2 Bit Internal Quantizers written by José S. Niell and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 1995 with categories.

Digital Calibration Algorithms For Nyquist Rate Analog To Digital Converters

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Author : Anup Savla
language : en
Publisher:
Release Date : 2004

Digital Calibration Algorithms For Nyquist Rate Analog To Digital Converters written by Anup Savla and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2004 with Analog-to-digital converters categories.

Abstract: Continuous scaling down of CMOS device sizes and an accompanied increase in device switching speeds prompts the design of mixed-signal systems with increasingly complex digital signal processing and control algorithms accompanied by simpler analog circuitry. Analog to digital converter (ADC) is an essential mixed-signal component of modern receivers, where signals sensed from the source are converted to digital for further signal processing on them. In this dissertation, calibration techniques are presented which allow ADCs to be designed with large inherent gain and offset errors. The concept of arbitrary radix multistep conversion is presented, along with algorithms that enable reduced radix conversion with digital correction in pipelined or algorithmic ADCs. Calibration techniques that account for linear and nonlinear gain error are presented and adapted to the popular 1.5 bit/stage pipeline architecture. Calibration is performed purely with digital post-processing on ADC output bits, with no changes occurring in the analog hardware. In this dissertation a WCDMA/WLAN receiver architecture is presented and specifications are derived for all its components. Concept of reconfigurable ADC design is presented, which allows speed and power consumption optimization. Reduced radix digital correction, linear and nonlinear calibration and background-calibrating queues are presented and combined in two behavioral models. The reconfigurable ADC was fabricated in AMI0.5u 3V CMOS process, and achieved 55dB dynamic range at 45MS/s, consuming 51mW power. The reconfigured calibrated ADC was simulated in TSMC 0.18u 1.8V CMOS process, and achieved 63dB dynamic range at 25MS/s, consuming 3.6mW power. Measurements of the capture card showed a 1.6bit improvement in resolution with the use of calibration algorithms.

Pipelined Analog To Digital Conversion Using Class Ab Amplifiers

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Author : Kyung Ryun Kim
language : en
Publisher: Stanford University
Release Date : 2010

Pipelined Analog To Digital Conversion Using Class Ab Amplifiers written by Kyung Ryun Kim and has been published by Stanford University this book supported file pdf, txt, epub, kindle and other format this book has been release on 2010 with categories.

In high-performance pipelined analog-to-digital converters (ADCs), the residue amplifiers dissipate the majority of the overall converter power. Therefore, finding alternatives to the relatively inefficient, conventional class-A circuit realization is an active area of research. One option for improvement is to employ class-AB amplifiers, which can, in principle, provide large drive currents on demand and improve the efficiency of residue amplification. Unfortunately, due to the simultaneous demand for high speed and high gain in pipelined ADCs, the improvements seen in class-AB designs have so far been limited. This dissertation presents the design of an efficient class-AB amplification scheme based on a pseudo-differential, single-stage and cascode-free architecture. Nonlinear errors due to finite DC gain are addressed using a deterministic digital background calibration that measures the circuit imperfections in time intervals between normal conversion cycles of the ADC. As a proof of concept, a 12-bit 30-MS/s pipelined ADC was realized using class-AB amplifiers with the proposed digital calibration. The prototype ADC occupies an active area of 0.36 mm2 in 90-nm CMOS. It dissipates 2.95 mW from a 1.2-V supply and achieves an SNDR of 64.5 dB for inputs near the Nyquist frequency. The corresponding figure of merit is 72 fJ/conversion-step.

Low Power High Resolution Analog To Digital Converters

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Author : Amir Zjajo
language : en
Publisher: Springer Science & Business Media
Release Date : 2010-10-29

Low Power High Resolution Analog To Digital Converters written by Amir Zjajo and has been published by Springer Science & Business Media this book supported file pdf, txt, epub, kindle and other format this book has been release on 2010-10-29 with Technology & Engineering categories.

With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. This has recently generated a great demand for low-power, low-voltage A/D converters that can be realized in a mainstream deep-submicron CMOS technology. However, the discrepancies between lithography wavelengths and circuit feature sizes are increasing. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. The inherent randomness of materials used in fabrication at nanoscopic scales means that performance will be increasingly variable, not only from die-to-die but also within each individual die. Parametric variability will be compounded by degradation in nanoscale integrated circuits resulting in instability of parameters over time, eventually leading to the development of faults. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods. In an attempt to address these issues, Low-Power High-Resolution Analog-to-Digital Converters specifically focus on: i) improving the power efficiency for the high-speed, and low spurious spectral A/D conversion performance by exploring the potential of low-voltage analog design and calibration techniques, respectively, and ii) development of circuit techniques and algorithms to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover errors continuously. The feasibility of the described methods has been verified by measurements from the silicon prototypes fabricated in standard 180nm, 90nm and 65nm CMOS technology.

Novel Architecture Of Analog To Digital Converter

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Author : Narula Swina
language : en
Publisher:
Release Date : 2023-02-28

Novel Architecture Of Analog To Digital Converter written by Narula Swina and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2023-02-28 with categories.

A number of digital applications e.g. professional cameras, voice communication, video digitizers, data imaging and many more require low power, high speed, and high resolution analog to digital converters. But for high speed data communication systems with increased resolution and high sampling rates, different linear and nonlinear errors of ADCs come in picture which is a big challenge for design engineers to remove.A unique digital background calibration technique, a combination of signal dependent dithering with butterfly shuffler is proposed here for multi-bit, SHA-less 16-bit, 125 MS/s Pipelined ADC. The purpose of the research work was to integrate different stages of different sizes to achieve 16-bit error-free output at high sampling rate by using unique background calibration technique for SHA-less circuit. Because the achieved values of SNDR and SFDR are high with low power consumption, so this proposed ADC is suitable for high resolution applications like video communication. Without using sample and hold amplifier we saved power and reduced noise interference. Additional advantage of SHA removal is to use a smaller input sampling capacitor which increases ADC's drivability. A new timing diagram is also proposed here to resolve the sampling clock skew. The ultimate multi-bit front-end proposed here helped to save further power.The proposed comparator is able to avoid the kickback as compared to traditional comparators. For the initial multi-bit stage, a two-stage gain boosted amplifier is used to achieve high gain and to reduce the nonlinear gain errors. Because the non-idealities of Op-amp and capacitor mismatching errors, the ADC transfer function may achieve erroneous values by DNL errors, so the proposed technique is made capable to remove linear gain and offset errors and capacitor mismatching errors. Also the small signal linearity errors removed with the proposed architecture of 16-bit Pipelined ADC. Along with these advantages, high values of SNDR and SFDR has achieved, which is a top most indicator to distinguish the signal out from other noise and spurious frequencies.

Background Calibration Of Timing Skew In Time Interleaved A D Converters

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Author : Manar Ibrahim El-Chammas
language : en
Publisher: Stanford University
Release Date : 2010

Background Calibration Of Timing Skew In Time Interleaved A D Converters written by Manar Ibrahim El-Chammas and has been published by Stanford University this book supported file pdf, txt, epub, kindle and other format this book has been release on 2010 with categories.

The increasing data rate of wireline communication systems leads to more inter-symbol interference, due to the dispersive properties of the communication channel. This requires more complex equalization blocks to meet the required bit-error rate. One solution is to use an Analog-to-Digital Converter (ADC) in the front-end, thus enabling a digitally-equalized serial link. To achieve the high-data rates of these communication systems, a time-interleaved ADC is typically used. However, this type of ADC suffers from several time-varying errors, the most prominent of which is timing skew. This thesis introduces a statistics-based background calibration algorithm that compensates for the effect of timing skew. To demonstrate the background calibration algorithm, a proof-of-concept 5 bit 12 GS/s flash ADC has been fabricated in a 65 nm CMOS process. The design of this ADC takes into consideration the tight power bounds imposed on serial links by optimizing both the time-interleaved and the sub-ADC architecture. Power consumption is further reduced by using calibration circuits to correct the offset of the flash ADC's comparators. In the measured results, the timing skew correction improves the dynamic performance of the time-interleaved ADC by 12 dB, and the proof-of-concept ADC has the lowest published power consumption for ADCs with sample rates higher than 10 GS/s.

High Resolution And High Speed Integrated Cmos Ad Converters For Low Power Applications

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Author : Weitao Li
language : en
Publisher: Springer
Release Date : 2017-08-01

High Resolution And High Speed Integrated Cmos Ad Converters For Low Power Applications written by Weitao Li and has been published by Springer this book supported file pdf, txt, epub, kindle and other format this book has been release on 2017-08-01 with Technology & Engineering categories.

This book is a step-by-step tutorial on how to design a low-power, high-resolution (not less than 12 bit), and high-speed (not less than 200 MSps) integrated CMOS analog-to-digital (AD) converter, to respond to the challenge from the rapid growth of IoT. The discussion includes design techniques on both the system level and the circuit block level. In the architecture level, the power-efficient pipelined AD converter, the hybrid AD converter and the time-interleaved AD converter are described. In the circuit block level, the reference voltage buffer, the opamp, the comparator, and the calibration are presented. Readers designing low-power and high-performance AD converters won’t want to miss this invaluable reference. Provides an in-depth introduction to the newest design techniques for the power-efficient, high-resolution (not less than 12 bit), and high-speed (not less than 200 MSps) AD converter; Presents three types of power-efficient architectures of the high-resolution and high-speed AD converter; Discusses the relevant circuit blocks (i.e., the reference voltage buffer, the opamp, and the comparator) in two aspects, relaxing the requirements and improving the performance.